| With the development of signal processing technology,how to reduce the power consumption of equipment is the main research problem in the process of design.Analog to digital converter(ADC)is an important part of most devices.It is a link between analog signal and digital signal conversion,and the power consumption of ADC affects the whole power consumption of the whole device.In many kinds of analog-to-digital converters,SAR ADC has been widely applied for a long time because of its simple structure,small area and low power consumption.So,its design technology is attracting more and more attention.In this thesis,a 10 bit low power SAR ADC is designed,which is composed of a digital analog conversion(DAC)circuit,a comparator and a SAR logic control circuit.DAC module uses a new DAC conversion network with segmented capacitor arrays to effectively reduce the power consumption and capacitance of the capacitor array;At the same time,the use of MOS tube constant current source at the top of the traditional comparator reduces the offset error and simulates its propagation delay and resolution.The logic control part of the SAR adopts a D flip-flop composed of a CMOS transmission gate and a NAND gate,which effectively saves the circuit area,reduces the power consumption,and performs simulation verification thereof.Finally,the SAR ADC integrated circuit is simulated,and the related performance parameters of SAR ADC are tested.The results show that the SAR ADC designed in this paper can meet the design requirements.Static performance parameters: the largest DNL is 0.23/-0.23 LSB,the largest INL is 0.27/-0.25 LSB,and the dynamic performance parameters are SNR=47.9 dB,SINAD=47.8 dB,ADC of SAR ADC.When the transient current is 300 μA,average power consumption is0.36 mW,which meet the design requirements. |
