Design Of All Digital Phase Locked Loop Based On MCML

Phase locked loop(PLL)is a circuit which can realize the automatic tracking of the output signal frequency to the input signal frequency.With the development of digital integrated circuit technology,all digital phase-locked loop(PLL)has attracted more and more attention because of its small size,strong anti-interference ability and easy to integrate with other digital modules.MCML circuit is a kind of configuration of MOS circuit,compared with the traditional CMOS circuit,has the advantages of low power consumption and strong anti-interference ability in the high frequency operation.Because of the small logic swing of MCML circuit,the logic conversion speed is faster than the traditional CMOS logic circuit.In this paper,the MCML circuit is analyzed,and the optimal design parameters of the logic gate circuit are obtained.The time digital converter of MCML structure mainly includes the design of time delay chain,D trigger structure and decoder structure.The aim of the design is to improve the resolution of TDC and increase the conversion speed of TDC.In this paper,the TDC of each module with Cadence Spectre simulation,in 0.13 ?m CMOS process,the resolution reached 20 ps,the conversion speed compared to the traditional CMOS structure has improved by 12%.In the design of MCML multimode frequency divider,the prescaler and the main divider is designed,the purpose is to reduce the power consumption at high frequencies.In this paper,the design of the MCML multi-frequency divider circuit is simulated,the results show that the power consumption is lower than the traditional CMOS structure,which is 31% of the traditional CMOS structure.At the condition of supply voltage is 1.2V,logic swing is 0.5V,reference clock is 60 MHz,multimode frequency division ratio is 40 times,the output frequency of all digital phase-locked loop is 2.4GHz designed by using SMIC 0.13 ?m 1P8 M CMOS process simulation and layout.The simulation results show that the power consumption of the All Digital Phase Locked loop is 26% lower than that of the CMOS phase locked loop with the same frequency,and the locking speed is improved by 17 ps.