Design And Validation Of Multi-bit Data Across Clock Domain Based On Digital Down Converter

In the modern ASIC and FPGA designing,with the increasingly complex of digital system,there may be ten millions of gates or more in a design.According to the different functions,it uses multiple clock circuits,and it would have a big difference in different clock frequency and phase,which are not the same clock.When transmitting data between two different clock domains,it may lead to data transmission error,metastable propagation and cause error function,even may cause whole system collapse.And for most of EDA tools,especially backend integrated tools,we can't make sure that the found dislocation is caused by a trigger in a metastable,which makes the design becomes unreliable when determining whether such an asynchronous signal satisfies the setup time and hold time of the trigger.Also,the clock domain does not belong to a new request,but with the clock domain becoming more common,more complicated and large scale,integrated with strict requirements for performance and frequency adjustment makes the clock domain design more and more important.Code designers need to put some kind of mechanism according to the specific requirements of the artificially,to ensure the correctness of data transmission,which is the main content of this article needs to discuss the clock domain signal synchronization.And it is main discussion of this paper.In such background,this paper firstly introduces three kinds of single bit across method.Then it introduces the method of multi-bit data across clock domain,including gray code,handshake signal,asynchronous FIFO and RAM,and analyzes their respective advantages and disadvantages.In this paper,based on the number of frequency conversion of the clock domain processing,digital frequency conversion design specification requirements under the link needs delay stability,adjacent frame head fixed for 10 ms delay and the system by the abnormal returns to normal.The system can also be quickly returned to normal,bits of data transmitting is important to synchronous clock domain in digital down-conversion across,when more bits of data across the clock domain processing.In the past,we usually use FIFO method in the design of asynchronous,but the FIFO can't appease the design demand of the delay stability,so this paper summarizes the existing across the clock domain synchronous processing method and the basis of a treated with RAM synchronization mechanism of the clock domain,which can be inferred by verifying well realize the function of realization,and simplify the complexity of used to deal with the logic circuit.It is concluded that different circumstances take different across different clock domain processing method to achieve the purpose that data transmission delay stability and periodic fixed.Specifically for the same design requirements,asynchronous FIFO and RAM are implemented across the clock domain separately.Asynchronous FIFO cross-clock domain processing includes asynchronous FIFO implementations,as well as read and write logic generation.The synchronous processing of RAM across the clock domain is primarily through reading the control that is written to achieve accurate data transfer.Finally through the verification,found that the asynchronous FIFO across the clock domain processing,can't meet the requirements of link delay stability,while the RAM can achieve good delay stability and fixed frame head cycle requirements.