The Research On Clock Domain Crossing Issues

By using of the EDA tools, the scale of modern ASIC or FPGA design could be ten million gates or more. But the Clock Domain Crossing issue (CDC) still can't be managed by tools automatically, which is the key point of this thesis. It is began with the overview of this CDC problem, discussed the advantage and disadvantage of each kind of synchronization mechanism by simulation. Especially, for the operations of different registers in the system based on ARM, a new synchronization method is implemented in this paper. At the same time, a new verification flow is created for the CDC issue. All of these methods and designs are proven by the silicon, so, this thesis is very useful for solving the CDC problems.