Font Size: a A A

The Study Of Synchronizer Design In Asynchronous Clock Domain System

Posted on:2008-04-30Degree:MasterType:Thesis
Country:ChinaCandidate:S PuFull Text:PDF
GTID:2178360212474918Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Designing multi-clock domain ASICs first should realize the stability in signal transmitting. It is a great challenge to a designer who is only familiar with the single clock-domain design. And that will case a unknown disaster if he did not pay enough attention to.This dissertation mainly researched on synchronizing data between asynchronous clock domains which came from the practical application. The major achievements are shown as below.1. The problem with transmitting single signals between asynchronous clock domains. Metastability could never been avoided in anytime when transmitting signals between asynchronous clock domains. But with some methods introduced in this dissertation, it could been decreased to an acceptable level. With the view of circuit system, expatiated how to use the handshake signal rules to connect each part of circuits in asynchronous circuits. After expounded the idea of data path design, analyzed two especial example in this condition.2. The problem with transmitting bus signals between asynchronous clock domains. Explained the advanced data path design idea with the example of asynchronous FIFOs. Asynchronous FIFO is an excellent solution to transmitting bus signals between asynchronous clock domains. But it also has some challenging difficulties, much more than metastability. In this dissertation, designed four kinds of general asynchronous FIFOs with RTL level design, function and behavior simulations, and gate level synthesis with the library of SMIC .25, at last of this part, analyzed their advantages and disadvantages in architecture and functions to give designers a clear thought to choose them.3. Successfully designed the buffer module in the"CFHC IP Core"project. The module is based on the architecture of two symmetrical asynchronous FIFOs to transmit data in and out separately to the purpose of transmit and buffer data and change the bit of data width.Above all, this dissertation researched on the synchronizer design of system in asynchronous clock domain from the theory, discussed the solution for some common problem as metastabiliy, race and hazard, empty/full flag generating and etc. Based on these therories and researches, the buffer module achieved the specification requiring...
Keywords/Search Tags:Data synchronization, Metastability, Handshaking signal, Asynchronous FIFO, Empty/full flag generating
PDF Full Text Request
Related items