Research On Clock Doiiiain Crossindesin

With the increasing complexity of digital system, a circuit system needs tocommunicate with other subsystems, but in most circumstances, each system ownsdifferent frequency and phase, which makes a series of problems when signals transfercrossing clock domains. Although clock domain crossing is not a new field to besolved, CDC is becoming more and more important as multiple clocks appear muchmore common and complex than ever before, coupled with large scale integration andthe stringent requirements of performance. In addition, considering the current EDAsoftware can not solve asynchronous signals crossing clock domains, synchronizationis neccessary for circuit including multi-clock domains in order to ensure that the chipcan reliably run through multiple asynchronous clock domains. This paper comes froma project of contact smart card chip in Beijing Hua Hong Semiconductor Co., Ltd andthe author independently finished the frond-end design of UART. To solve the problemof CDC, this paper, firstly, analyzes the problems encountered when datas transmitfrom one clock domain to another asynchronous clock domain. Then, based on that,this paper systematically describes several different mechanisms of data transmissionthrough different clock domains, and presents a series solutions in various levels ofcircuit design and analyzes the characteristics of different synchronization mechanisms.Last, based on the theory above, this paper finished UART coding with verilog. Duringthis process, different kinds of datas to be transferred between two asynchronous clockdomains are classified and solutions of synchronization of UART module based on51embedded systems are proposedk. The front-end design of UART is verified itsfeasibility through simulation with VCS simulator.