PCM Module Design And Clock Domain Crossing Analysis

With the increase in the scale and complexity of integrated circuits,the number of clock domains in the chip is also increasing,which makes the clock domain crossing analysis increasingly difficult,and also brings greater challenges to the reliability and stability of the chip.Because the signal transmission across the clock domain may cause metastability,data loss and other faults,and these faults usually propagate and spread to the subsequent circuits,causing a large range of circuit paralysis.Therefore,for circuits with multi-clock design,a complete clock domain crossing analysis is essential.In this paper,the RTL-level circuit design is carried out according to the design specifications of the PCM module,and the Bluetooth audio transmission module used between the radio frequency circuit and the application processor is implemented.It supports Bluetooth audio transmission in Linear / A-law / U-law / I2 S four audio formats and has audio data compression,decompression and gain functions.Then use SG Lint to check the syntax and semantics of the RTL circuit of the PCM module to ensure the quality of the code,and at the same time use Questa sim to carry out pre-simulation to ensure that the circuit functions correctly.This paper analyzes the problems that may occur in the design of the chip using multiple clocks,introduces common clock domain crossing synchronization schemes and transmission protocols,and proposes a clock domain crossing analysis process that combines static analysis and dynamic analysis.Starting from the three aspects of synchronizer structure,synchronizer transmission protocol and re-aggregation,three methods of static analysis of circuit structure based on Questa CDC,dynamic simulation based on assertion and functional simulation based on metastable injection are used for clock domain crossing analysis.Based on the above three clock domain crossing analysis methods,the clock domain crossing analysis of the PCM module is completed from four aspects: environment construction,process introduction,inspection report analysis,and circuit optimization.After design and debugging,the PCM module successfully passed the syntax,semantic check,and pre-simulation,showing that it correctly realized the expected function.During the structure analysis phase of the synchronizer,a total of 96 clock domain crossing paths were checked by optimizing or redesigning unreasonable synchronization schemes and cleaning up false positive information.Among them,there are valid synchronizers in 78 clock domain crossing,and the remaining 18 clock domain crossing signals are written through the RISC protocol,marked as exempt types,and pass static analysis.During the analysis phase of the synchronizer transmission protocol,by optimizing the circuit function,the assertion coverage rate was successfully reached 100%,which ensured that all synchronizers had valid data transmission during dynamic simulation,and the corresponding transmission protocol was not violated.In the analysis stage of the reconvergence problem,the introduced metastable injection model injected the metastable state multiple times in 16 single-bit data synchronizers,and the circuit function was still correct.The work in this paper not only guarantees the reliability of data transmission in the PCM moduleclock domain crossing,but also proves that the analysis method proposed in this paper is feasible and effective.