Design Of H.264 Decoder Based On FPGA

With the advent of multimedia,video has become one of the main ways to obtain information in today's society.As our need for video resolution and frame rate develops,the high quality video has a high demand for the storage system and the transmission channel.So it is very important to select the video codec standard.In order to realize the real-time decoding of high quality video,this paper chooses FPGA to implement the decoder design of H.264 codec standard.First of all,this paper introduces the related concepts of H.264 codec standard,compares the advantages and disadvantages of various decoding methods.Then analyzes the H.264 codec structure and processes,and the decoder is divided into four modules: entropy decoder,inverse quantization and inverse transform decoder,intra prediction decoder and inter frame prediction decoder.Secendly,this paper optimizes each decoder module.The grouping calculation method is used to reduce the times of look-up tables and the depth of the traversal.In the inverse quantization and inverse transform decoder,the two-dimensional inverse transform is converted into two onedimensional butterfly operations,which reduces the complexity of the algorithm.By using 4 reconfigurable computing units,the seventeen prediction modes of intra prediction are unified to save resource.Four pixels intra prediction decoding can be achieved in each clock cycle.Inter prediction coding use motion vector to locate the reference pixel,then interpolate prediction pixel value.Finally,the four decoder modules are integrated with the state controller,and the function of each module is realized.Verify the proposed decoder on Altrea IV EP4CE40F23C8 N platform.Use Quartus II to synthesize the whole design and simulate under the environment of Modelsim.The performance of the decoder is analyzed by using the method of black box verification and JM86 as the reference model.The result shows that the peak signal to noise ratio is about 40 dB.When the decoder runs at the highest frequency,it can complete the real-time decoding of 720@30fps video.The design can support the baseline profile of H.264 decoding standard.