DCT And IDCT Circuit Design And Its FPGA Implementation For Video Codec

Video and Image compression standard, such as MPEG-1/2/4、H.264 and VC-1, are widely used in video and image applications. In this thesis, multi-level factor share and distributed arithmetic are being used to build multi-standard DCT(Discrete Cosine Transform)and IDCT(Inverse Discrete Cosine Transform)transforms. The proposed architecture can process four transform types, including 8×8、8×4、4×8 and 4×4 transforms. We use multi-level factor share and distributed arithmetic to share the coefficient matrix circuits and we replace the multipliers with the adders and shifters. The result not only reduces the number of redundant parts in coefficients multiplication, but further reduces the needed adders in adder trees and leads to a low-cost design. Besides, based on the similarities of DCT and IDCT transforms, we reuse the same circuits to manipulate DCT and IDCT by interlaced sorting methods. Not only the cost of area is saved, but DCT and IDCT are also operated simultaneously to reach the high throughput rate and meet the demands of real-time system. By using the transpose memory, we are able to transpose the 1-D results into the 2-D input data. With SORT1 and iSORT1 circuits, we further arrange the data of 1-D and 2-D in orders which will allow us to reuse the same 1-D core to compute 2-D data. That means we can compute DCT and IDCT’s 1-D and 2-D data in the same time with only one 1-D core. Design of DCT and IDCT arithmetic circuit was functionally verified on the FPGA, carried out using the ModelSim simulation waveforms, and used Matlab to calculate the theoretical value as verification model, the simulation results using some current standard specification parameter to characterize the accuracy of the algorithm, indicating that the design of the circuit can be completed the program design features, and the basic indicators meet current standards.