Study And Implementation Of H.264 Decoder Based On FPGA

With the rapid development of digital video technology and computer communication technology, video communication has become the focus of recent research. Video codec algorithm selection is particularly important in video signal transmission as well as storage. As our need for resolution ratio of video develops, we also make higher and higher requirement for real-time video decoding. Therefore, the design of real-time H.264 decoder is particularly important. In order to achieve this goal, this design chooses FPGA to complete the design of video decoder.In the first place, this paper describes the video codec standards’ development process and the decoding process of H.264. On the basis of deep analysis on the H.264 decoding process, the decoder is divided into several major functional modules, including entropy decoder, coefficients-transform decoder, prediction data decoder and block filter decoder.Secondly, focus on the entropy decoder to optimize the design. We proposed a dual amplitude entropy decoding structure based on prediction method. This design approach introduces a prediction module to break the data dependency when decoding. The results show that this double amplitude entropy decoder can save 26% of the computation time than traditional implementations.Then, complete design and implementation of the coefficients-transform decoder, predictor and block filter. The coefficients-transform decoder uses reconfigurable architecture implementation. The predictor combines both intra-frame prediction and inter-frame prediction. The block filter uses a five pipeline implementation.Then, the bit stream buffer is designed to reduce the frequency at which decoder reads data from the external memory. In addition, syntax elements parser uses the implementations to decompose complex state machine into sub state machine. Design of the bit decomposition state machine stream can not only simplifies the design process,but also can reduce power consumption of the decoder by 34%.Finally, verify the proposed decoder on XC500VFX200 t platform. Use ISE13.2 to synthesize and simulate the whole design. The results show that the decoder totally consumes 5% register and 21% LUT of FPGA. Maximum operating frequency of decoder is 216 MHz. Analysis under the condition of 50 MHz showed that the throughput of binary code stream decoding is 960 Kbps. Decoding a macro block requires 577 clock cycles on average, that is, decoding a macro block needs 11.54 us. For 4CIF(704 * 576 @ 30fps) H.264 Baseline level video formats, only a clock as slow as 27.4MHz is enough to complete real-time decoding.