Hardware Design And Implementation For H.264 CAVLC Decoder

With the rapid development of science and technology, image has become one of the most important objects to carry information, but both the image and video have enormous data which brings difficulties for storage and transmission. Therefore, the process, encoding and transmission of multimedia, especially image, are taken as advanced issue in the field of information and telecommunication.H.264 was published in 2003 and is excellent in the encoding-rate, network-adaptability, error-resilience. Compared with the previous recommendation, it gains better compression and quality with the same encoding-rate.The paper introduces the key technologies of H.264, including intra-prediction, inter-prediction, transform and entropy-encoding as well as deblocking filter. On the base of the deep research of CAVLC, hardware architecture of FPGA+DSP is presented. According to the codes' property of CAVLC, the paper describes CAVLC decoder by using finite state machine to control the decoder flow and optimization of code-table search to increase the speed. Simulation results testify that the design can realize real time decoding different format streams.