Based On The Research And Verification Of Fpga H.264 Decoder

H.264 video coding standard is the newest generation of video coding standard which is surporrted by International standard organization and ITU-T and many other leading Company.It has high coding efficiency compare to its processator like divX. The video file size is less than 70% of the file with divX coding. On the other hand, H.264 encoder and decoder consume much more resources, which made it a challenge to mainstream gernearal processor. One of the solution is design a decoder with high performance per clock on FPGA or ASIC. The other way is to increase parrallel processing module to double the decoding performance.In this paper, a high efficient H.264 decoder based on FPGA was presented. It has been optimized with multi-bit "1" detector, transformation module multiplexing and high-efficiency look up table in CAVLC decoding process. The decoder was designed with verilog-HDL and tested on FPGA with official test sequence.For QCIF resolution video, this decoder can work at clock frequency as low as 1.8MHz, which proved to be efficient in each clock. The CAVLC decoding module can work at as high as 150MHz and can process video with resolution up to 1680x1050. However the intra frame prediction cost so many resources and the overall decoder can work at 80MHz. It can handel 1280x800 resolution video. In this paper, SDRAM controller and VGA adaptor was also considered as peripheral module.