Research And Implementation Of H.264 Decoder Based On FPGA

Recently, with the development of broadband and multimedia processingtechniques,video compression technology has become a hot topic. With thedevelopment of the complexity of encoding and decoding algorithm, H.264/AVC,featuring large volume of data in this paper particularly, will be very slow in thereaction progresses with the common software. What's more, apart from the high price,ASIC lacks the flexibility, versatility and scalability and involves a range of issues likeintellectual property rights, etc. It is of great significance both in practice or intheoreticalresearchforthedesignofcodinganddecodingbasedonhardwareplatform.This paperaccomplishs the hardwaredesignof severalkeytechnologydecodersofbaselineprofileofH.264/AVCDecoder andtheframeofH.264/AVCDecoder.Andthenthe paper simulates the decoder on PC. Fillay this paper manages the displaying ofvediofromH.264/AVCdecode.Firstly, this paper introduces the development of the principle of video coding andseveral ways of video coding.So the significance of research in this paper is claimed.And then it simply discusses the principle of video coding with the focus on theoverview of H.264 standard including the processes of coding and decoding,mainframework and specific technologies and so on.This paper is based on thesecontent.Then this paper introduces the technology of FPGA and the principle anddecoding processing of CAVLC, Intra Prediction, Inter Prediction and De-blocking inH.264/AVCofbaselinelevel.Basedonthesetheories,thepaperelaboratesthedetailsofthe processing of hardware design of those key technology decoders, giving their codemodule frames and result of synthesizing. Besides, based on the principle of H.264standard, this paper brings up the hardware design of H.264/AVC decoder, and thenthrough the simulation verifying and the synthesizing. The paper analyzes itsperformance elementarily. After giving an introduction of the FPGA platform used inthis paper, several Key Technologies during the processing of H.264/AVC decodingtransplant are elaborated . Finally this paper manages to display the digital video fromH.264/AVCdecoder.The design of H.264/AVC decoder in this paper is not optimized, and it is onlyused for QCIF video stream to decode now. With the limited time and the help ofsoftware toshift the code stream byUSB Blaster, H.264/AVC decoder fails totransportcode stream through Ethernet port. The next aim is to improve the program and perfectthe frameworkofsystemonFPGAplatformsoastorealizetheencodinganddisplaying of SD and HD video based on this FPGA platform.