.h.264/avc In Cavlc Encoder Hardware Design And Fpga Implementation

H.264/AVC, the next-generation video coding standard, is jointly developed by the ITU-T and the ISO/IEC. It has higher compression efficiency and better network-adaptability than previous standards. CAVLC is one of significant technologies to raise the performance of H.264/AVC, but its software realization is hard to satisfy the requirement of HD video real-time codec. This thesis studies the principle and technical characteristics of CAVLC; takes advantage of the features of high speed and real time of FPGA; modifies the serial encoding model of software and designs a hardware CAVLC encoder. The designing system adopts the parallel and pipeline processing architecture to encode all syntactic elements concurrently; processes the level encoding module, which has the biggest complexity and the longest delay of CAVLC encoding modules, in parallel with the efficiency of encoding 2 level values per clock cycle; and introduces the signal of effective tag and codeword length to control the sub-module and codeword respectively. The circuit is generated through Verilog HDL, simulated in ModelSim SE 6.0, implemented and verified by VirtexⅣxc4v55 FPGA of Xilinx. The result shows:the same output as JM16.2 with the same input, costing 262～276 clock cycles to encode a 16x16 macro block and supporting the real-time CAVLC encoding of 1920x1080@60fps video streaming at 372.2 MHz with limited resources consumption. It has Practical value in engineering application...