Cavlc Decoder Hardware Architecture And Design

H.264is regarded as the next generation video compression coding standard since published in2003. Because of its high compression ratio, low transmission ratio and good image quality, H.264attracting more enterprises in the field of network, streaming media and mobile media. More and more domestic and foreign corporations introduce the H.264standard in their products. With the demand of market and technology development, in the year of2003,2005,2009and2010, the published H.264standard contains more clauses, extensive application and enhanced application levels. High quality image, HD video and low-power mobile terminal challenge the video compression encoding and decoding. H.264does not specify the implementation of the specific encoder and decoder, but defines the syntax element and describes the method of encoding and decoding. So researchers need to complete the design and architecture themselves. On this basis, CAVLC module of the H.264decoding system is studyed and implemented in this paper, relevant technology and algorithm introduced.The detailed work includes the following aspect.(1) System strcture:here the system includes Exp-Golomb decoding module and CAVLC decoding module. It can decode macroblcok layer parameters and residue data, and be capable of sequential decoding.(2) CAVLC decoder optimization:combining the level and trailingones decoding state, optimizing the H.264CAVLC algorithm. Using pipeline operation for level decoding and level-run matching, which allocates the clock cycles in a efficient way and shortens the critical path delay. By predicting level length and run length, multi-level and multi-run can be parallel decoded in the same cycle. Proposed design efficiently decreases the cycles. For full I frame sequence with QP28decoding (Akyio, foreman, hall, container), the average rate is97MB/cycle.(3) CAVLC chip architecture and implementation:system designed using verilog language and simulated by Modelsim software. At the beginning, it was designed and synthesized in Quartus Ⅱ software with selected device EP2C70F89C6, then synthesized by synopsys DC compiler with TSMC18technology. The frequency of CAVLC decoder can reach152Mhz. Testing the1080p YUV sequence like blue-sky, system can fully meet the requirement of level4.11080p30fps real-time decoding.