Research And Implementation Of Scalability On FPGA Reconfigurable Computing

With the rapid development of information technology,the amount of information also has an increasing tendency because of a rise of some hot industries such as Big Data,Internet of Things and Artificial Intelligence.These hot industries stimulate an urgent demand for high-performance processing technology.However,due to the limitation of semiconductor technology,the performance of the processor has been difficult to meet the needs of high performance computing,so it is replaced by a homogeneous multi-core processor such like multi-core,many-core.Whereas,once computing performance of homogeneous multi-core processor reache the limit,its computing ability will no longer be increased even if the number of core is added.It's been researched that the heterogeneous multi-core processor with CPU and FPGA can meet the need of the calculation efficiency in Big Data,with low power consumption.However,although the CPU-FPGA heterogeneous system has good advantages in the field of high-performance computing,it has not been applied in a large scale.One of the main reasons is that the development efficiency of FPGA is lower than that of the general computer system and another is the poor scalability of FPGA computing mode.Subjectd to the physical resource in devices,if the developer does not provide the source code,it is difficult to deploy application to different FPGA devices for users.It will limit the large-scale propagation and application of the achievements.Based on the dynamic partial reconfiguration technology and the virtual storage pool mechanism,the paper realizes a scalability mechanism about reconfigurable computing on FPGA.The main implementations include:the FPGA resources are divided into physical resources and logical resources,users who just need to meet the demand of logical resources will not be restricted by physical resource when the develop an application on FPGA.Depended on page rank,compatibility between pages and combination transfer,a hierarchical fixed page partitioning mechanism can be put into use in order to adapt a variety of applications.Pages implement two communication modes: the shared memory and pipeline.In addition,in order to promote the large-scale application of FPGA,and improve the efficiency of development.This paper provides a set of development models based on the design reuse and decoupling ideas,encouraging developers to share FPGA application results,and making it convenient for users to develop an application and experience the high-speed performance.The scalability architecture of FPGA reconfigurable computing in this paper can support SIMD/MIMD parallel computing mode in FPGA.It can also support pipeline mode through communication of reconfigurable units,which is convenient for users to select the corresponding calculation mode according to the specific application,and achieve the maximum computational efficiency.The experimental results show that compared with other platforms and traditional FPGA applications,the architecture can simplify the user's programming mode effectively while maintaining the high performance and low power consumption of FPGA computing system,which is helpful to promote the large-scale dissemination and application of FPGA results.