Module-based Partial Reconfiguration And Application Research

Reconfigurable computing is a novel computing diagram in the temporal-spatial domain. It depends on the reconfigurable character of reconfigurable logic devices. Reconfigurable computing system can execute the task likes processor for higher flexibility, and likes ASIC for higher performance, so it is the hotspot of current high-performance computing research field. Partial reconfiguration can reconstruct partial logic resources on the reconfigurable logic devices without influence of the circuit functions on the rest part of the reconfigurable logic devices, in order to achieve time division multiplexing the reconfigurable logic resources. Partial reconfiguration can achieve higher performance and resource utilization.For reconfigurable computing technology, especially the partial reconfigurable technology has got more and more attentions. Some foreign universities such as University of Washington, the University of Toronto study in this area has been relatively in-depth, there is also a lot of excellent papers. However, the domestic research in this area has just started, but also requires a lot of manpower and resources to achieve achievement.Associating with the pre-validation study of "new type of high-performance reconfigurable supercomputer system",which is the special sub-major subjects of "high-performance computers and its core software" in the National 863 Program. Based on analysing the features and advantages of partial reconfigurable technology, learning from Xilinx modular design methodology. This paper offers a design flow of the Module-based partial reconfiguration, applies the design flow to the pre-processing module of MD5 and SHA-1 algorithm which are most commonly used in the network information security. The comparisons in the experimental results of suggested method with those of others demonstrate its effectiveness and show that the partial reconfigurable computing system can reduce the resource cost, and improve the reconfiguration performance effectively. In addition to meet the project's needs, the significance of this paper is also providing a reference and draw to the follow-up project implementation in related fields, and laying the foundation for the next research and improvement. This article has completed the following tasks:1,Based on Xilinx modular design methodology, the paper offers a design method of the Module-based partial reconfiguration.2,The article completed analysis and hardware design of the MD5 and SHA-1 hash algorithm. Parallelization and partial pipelining flow technology has been used in the design to optimize the operation of the algorithm operation tree.3,For the similarity of pre-processing module between the MD5 and SHA-1 algorithm, the design method of the Module-based partial reconfiguration has been applied.