Design Of A Partially Reconfiguration Platform And Study On Algorithms For Finding Empty Space

Nowadays, with the complexity required by embedded system increasing, hardware transistor density is also increasing. In this case, SoPC design methodology base on FPGAs is booming, moreover, system design level technology-reconfigurable computing gained more concern from academia.Dynamic Partial Reconfiguration (DPR) is a novel technique in reconfigurable computing. Taking advantage of DPR, system can independently configure a portion of specific computing resources in configurable devices without affecting the execution of other part. Compared with the configurable technique in early age, this reduces the overhead introduced by bitstream downloading and reconfiguration. DPR could gain better area saving and resource utilization and improve the overall performance of system.DPR platform in Virtex-4 which supports hardware task loading and scheduling is used for verification. This thesis details the construction of Virtex-4 DPR platform and the solution in design flow, further more, it conducts the comparison among several different solutions, describing some critical technologies and implementations. Finally, a series of experiments has been carried out on this platform. According to construction and implementation of such platform, we checked the feasibility of our solution so as to lay the first stone and accumulate a lot of experience for the further research and design. More importantly, platform provides the environment for testing hardware task scheduling algorithms, and makes the evaluation of scheduling algorithms more trustable and more accurate.Not only considering the temporal management, hardware task scheduling brings the new problem-spatial management. This thesis concentrates on searching free area in 2D model. By using some concepts such as valley point and threshold, the algorithm proposed in this thesis eliminate the redundant of previous stair-case algorithm and improve the algorithm efficiency.The current experiment results presented in this thesis guide the further research on performance evaluation of hardware task allocation and scheduling algorithm in DPR, and provide some theoretical basis for 2D area management.