Fpga-based Reconfigurable System And Cad Technology Research

As a new computing architecture, reconfigurable computing can achieve potentially much higher performance than software, while maintain a higher level of flexibility than hardware, so it has become a hotspot of current computer architecture research field. Because the development of reconfigurable systems is still a maturing field, many problems need to be sloved. One problem is absence of computer-aided design and compilation tools that conveniently map an application to a reconfigurable computing system, including task partition and mapping. Another key problem is how to reduce the reconfiguration time to increase the performance of reconfigurable system. This paper focuses on these problems, and the main works are shown as follow:Firstly, a reconfigurable system prototype platform is designed by using Xilinx Virtex-4 FPGA. This platform is used as the hardware base to research operating system supporting for reconfigurable computing and other applications. The function of this platform,the configure technique,system architecture and design flow are introduced in details in the paper.Secondly, a partitioning algorithm is proposed to partition an entire hardware task into interconnected subtasks for reconfigurable computing. The algorithm, called PCGA, syncretizes probabilistic constructive (PC) algorithm and genetic algorithm (GA). A new approach is proposed to measure the variety of partitions, and an initial population with a variety of better individuals is produced by PC algorithm. Then, the optimal solution is captured by GA based on these initial population.The experimental results show that PCGA can get better results of graph partitioning than those list-based partitioning algorithms; for the same solution quality, the PCGA has short execution time and it is discovered that the bigger the size of partitioning problem is, the better the PCGA performs.Thirdly, the reconfiguration time of FPGA-based reconfigurable systems is directly related to the size of the reconfiguration bitstream. In order to reduce reconfiguration time, a placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm aims at LUT-based FPGAs, and is modified on the existing placement algorithm within VPR. Besides the connection length and the critical path delay, it also introduces the LUTs configuration of the previous circuit into cost function to reduce the difference of LUTs configuration for subsequent circuits at the layout level. By using difference-based partial reconfiguration design flow, the proposed approach is validated by experiments. The experimental results show that the size of reconfiguration bitstream can be reduced, and consequently, the reconfiguration time is reduced.Finally, in order to reduce reconfiguration time, a routing algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. Besides considering the factors of effectively using FPGA routing resources and minimizing critical path delay, the algorithm also considers the relation of routing resources used by subsequent circuits. By making the most of routing resources that have been used for the previous circuit, the algorithm reduces the configuration difference of routing resources between subsequent circuits. Because about 70-90% of configuration bitstream relates to routing resources, by using difference-based design flow, the algorithm can effectively reduce the size of reconfiguration bitstream. The algorithm is modified on the existing routing algorithm within VPR, and experimental results show the availability of the algorithm.