The Research On Self-Reconfiguration Supporting Transparent Programming In Reconfigurable Computing

Reconfigurable computing using programmable hardware promises an intermediate tradeoff between flexibility and performance and becomes an impressive platform that can satisfy the requirements of embedded system applications. More recently, there has been an increasing study in the reconfigurable computing. With the development of programmable logical design technique, the programmable devices begin to support partial and dynamic reconfiguration. This provides a platform on which users can create a self-reconfigurable system that can change parts of itself at run-time. Such self-reconfigurable system generally contains microprocessor as the primary controller of the system and several reconfigurable hardware blocks as accelerators, forming a mixed software-hardware system. In the traditional method to program for such self-reconfigurable system,the programmers have to know the details of hardware accelerators, and control the configurations of hardware accelerators as well as communications between software and hardware parts. This state-of-art programming style is not efficient for system development. In this thesis, a transparent hardware-software co-design programming model is proposed. It hides the details of hardware and provides an easy-to-use interface to the programmers. How to support this transparent hardware-software co-design programming model in the self-reconfigurable system is studied.A transparent hardware-software co-design programming model for self-reconfigurable computing system is proposed. It contains three layers: a self-reconfigurable hardware system which supports the transparent programming model, the hardware functions which encapsulate the reconfigurable hardware accelerators, as well as an embedded operating system which supports the calling of hardware functions. A self-reconfigurable architecture is proposed. The microprocessor (fixed part) and hardware accelerators (reconfigurable parts) are regarded as a shared-memory heterogeneous multi-core parallel processing structure. The relation between the different parts and the implementation of the architecture are discussed in detail. The design and implementation of the bus connecting the fixed part and reconfigurable parts of the system are studied. A self-reconfigurable system design flow using Xilinx development tools is proposed. A self-reconfigurable system that contains several hardware accelerators and the corresponding hardware functions is created based on the above design flow to validate the feasibility of the proposed transparent programming model.The experiment shows that it is possible to implement a complex self-reconfigurable system in single FPGA chip based on the self-reconfigurable system deign flow discussed in this thesis. By adopting the transparent programming model, what programmers need to do is to call a hardware function while the system automatically reconfigures the corresponding accelerator and controls it to finish the computing task. This is helpful to increase the design efficiency of whole system.