System Based On Fpga Reconfigurable Chip

Due to dramatically increasing development cost, shorter time to market and flexibility demand, ASIC designs are more and more difficult. Meanwhile, reconfigurable devices are developing fast because of its flexibility and less development cost. But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations. So people began to consider combination of ASIC and reconfigurable device on a single chip, which is SOPC. SOPC can not only decrease development risk and timing to market, but also can be used in different applications, especially of products that keep varying, for example, communication and network products.Dynamically reconfiguration means reconfigurable device of the chip can be reconfigured repeatable, and performs different functions at different times. Compared with static reconfiguration, dynamic reconfiguration can use the reconfigurable device more thoroughly. It's a hot research in the world, especially in reconfigurable computing. This technology has developed a lot in theory, but it still has many deficiencies.One of the futures of FPGA development group is to design a SOPC chip that can support dynamic reconfiguration, which is a very big project. Work of this paper is part of this job. The research can be divided into two parts. The first part focuses on design of a universal SOPC chip. The second part is dynamic hardware platform for a specific application.Following work is done:1. Proposes a primary hardware platform of SOPC, problems in future design, and next a flow to solve the problem, also research of dynamic reconfiguration. Clear of what consist in dynamic reconfiguration and the steps to develop a dynamic reconfiguration system from the very front end of high level language description to mapping to the device.2. Consider of hardware design for a specific application, finally discrete wavelet transform is chosen. A reconfigurable hardware platform is proposed. Results show it's a high efficient and high speed design.3. Row module design of the discrete wavelet transform platform adopts idea of dynamic reconfiguration. It can save hardware area at no speed decrease.