Research On The Key Technologies Of Partial Reconfigurable Computing System

Reconfigurable computing is a novel computing diagram in the temporal-spatial domain. It depends on the reconfigurable character of reconfigurable logic devices. Reconfigurable computing system can be programmed likes processor for higher flexibility, and can execute the task in hardware mode likes ASIC for higher performance, so it is the hotspot of current computer architecture research field. As the most important development tendency of reconfigurable computing technology, partial reconfiguration can reconfigure a part of resources of reconfigurable logic device while the remainder continues to operate. Comparing with the former reconfigurable computing technology, it has better temporal-spatial domain computing characteristics and can effectively improve execution performance, resource utilization and reconfiguration flexibility of reconfigurable computing system.Nowadays, reconfigurable logic devices have provided plenty of supports for partial reconfiguration, but lack of corresponding design method badly restricts the application range of partial reconfiguration. To find a more general, and of course easier and more efficient solution to use of partial reconfigurable technology, this dissertation presents a module-based partial reconfiguration design method. This method partitions the application into the reconfigurable modules and fixed modules firstly, then designs each module by using modular design methodology, and finally implements the run-time partial reconfiguration in actual devices. By using foregoing method, several important encryption methods are implemented, and some related key technical issues such as cooperation between modules, communication channels design and timing adjusting scheme are resolved in this dissertation. The comparisons in the experimental results of suggested method with those of others demonstrate its effectiveness and show that the partial reconfigurable computing system can reduce the resource cost, and improve the reconfiguration performance effectively.Like all the other reconfigurable computing systems, reconfiguration process is a serious performance bottleneck of partial reconfigurable computing system, and the configuration cache is one of the most effective solutions to decrease it. The configuration cache technology of partial reconfigurable computing system is different from the cache technologies in the traditional computing systems because of its temporal-spatial domain computing characteristics. This dissertation presents several configuration cache replacement strategies of partial reconfiguration process based on penalty functions which composed of the historical execution information and the size of configuration data of task. Comparing with the former strategies, the algorithms in this dissertation have better tradeoff between LRU and LFU, so that they can make an optimal replacement decision. Simulation experimental results demonstrate the effectiveness of the replacement strategies that they can reduce the number of replacement process and economize reconfiguration time.With the development of semiconductor technology, the current reconfigurable logic devices have integrated millions of basic logic gates and plenty of specific coarse-grained computing logic units. Especially, the reconfigurable logic device with embedded processor makes the new self-reconfigurable computing system attract the wide attention. Self-reconfigurable computing system uses the specific circuits in the reconfigurable logic device to control the reconfiguration process of the device itself without calling for other extern configuration ports, so it can improve reconfiguration performance and reduce the related peripherals. Because the existing design process of embedded system based on reconfigurable logic devices is not suitable for developing self-reconfigurable computing system directly, a new method which integrates existing design process and module-based partial reconfiguration design method is presented in this dissertation. In addition, this dissertation does some researches on how to select the proper hardware IPs to meet the requirements of system design and the key issues of how to drive the internal configuration access port of reconfigurable logic device while the reconfiguration process is running. Experimental results demonstrate the method is effective, and also reveal the benefits of self-reconfigurable computing system.The novelties and contributions of this dissertation are:1) Presents a module-based reconfiguration design method, and implements several important encryption methods by using module-based partial reconfigurable computing technology for the first time. The method is feasible and useful, and has a good versatility. 2) Presents several configuration cache replacement strategies of partial reconfiguration process which put the historical execution information and the size of configuration data of task into the same replacement penalty function. The strategies can reduce the time cost of configuration cache replacement effectively.3) Presents a self-reconfigurable computing system design method which integrates existing design process of embedded system based on reconfigurable logic devices and module-based reconfiguration design method, and implements a self-reconfigurable computing system with dynamic reconfiguration ability.