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VLSI Design Of Bitplane Encoding In CCSDS Image Compression Algorithm

Posted on:2018-01-01Degree:MasterType:Thesis
Country:ChinaCandidate:C R WuFull Text:PDF
GTID:2348330515959903Subject:Computer application technology
Abstract/Summary:
Remote sensing image is one of the most popular methods of obtaining information for mankind.In recent years,with the rapid development of sensor technology,the amount of spaceborne remote sensing image data is increasing exponentially.However,due to the limitation of satellite-borne system resource and the downlink bandwidth,image compression is indispensable.In 2005,the Consultative Committee for Space Data System(CCSDS)released a new generation of spaceborne image compression standard,CCSDS 122.0-B-1,which adopts wavelet transform technology and Bitplane Encoding scheme.This standard supports lossless image compression and lossy image compression with variable compression ratio,and it has lower design complexity under the premise of considering the compression efficiency.It is an excellent image compression algorithm applied to Spaceborne Platform,which has good research value and application prospect.On the basis of in-depth study of CCSDS standard,the image encoding system is designed with Verilog HDL language in this paper.In the VLSI implementation of the algorithm,the Bitplane Encoding Module is the key of resource consumption.In this paper,a new Bitplane scanning scheme is implemented and the original serial scanning is improved as parallel scanning.With the new method,the scanning time consuming is decreased and the compression efficiency is improved.In this paper the VLSI implementation architecture of CCSDS algorithm is designed and simulated.The main work of this paper is as follows.(1)With the in-depth study of the CCSDS 122.0-B-1 Standard,the process of image compression algorithm is analyzed,and the encoding of DC coefficient and AC coefficient is discussed in detail.(2)Based on the CCSDS algorithm,the optimal design is carried out,and the original serial scanning is improved as parallel scanning.(3)The interface module and encoding module of image compression system are designed with Verilog HDL,including the image preprocessing module,the DC Coefficient quantization encoding module,the AC Coefficient Depth encoding module and the AC Coefficient Bitplane encoding module.(4)Simulating the function of Image Encoding System with Modelsim to validate the rationality of the system.
Keywords/Search Tags:Image Compression, CCSDS, FPGA, Bitplane Encoding, Parallel Scan
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