Design Of ESD Protection Circuit For Nanometer SRAM

As the feature size of semiconductor devices continues to shrink,the design of ESD protection circuits becomes more and more complex.Therefore,it is important to provide good ESD protection capabilities for advanced nanoscale chips.The main task of this paper is to design an ESD protection circuit for a nanoscale SRAM chip to ensure that its ESD protection capability is 2k V through the human body model(HBM).Firstly,the clamp circuit between VDD and VSS power lines was designed and simulated under nano-scale process.Secondly,the ESD bleeder channel is designed between different types of PADs of the SRAM chip to ensure that the ESD current can be rapidly discharged when the ESD occurs.Finally,a full-chip ESD protection circuit and layout are designed.The main innovations in this article are as follows:1)The clamping unit between the VDD and VSS power lines in the nanoscale process is designed.Firstly,the disadvantages of the clamping unit between the VDD and VSS power lines unit under the large-size processa and the traditional conduction clamp are analyzed,and a new ESD protection circuit suitable for application in the nano-scale process is designed.Secondly,we simulated the design of the new clamping unit,mainly include: when the ESD event occurs,the clamping voltage at both ends of the ESD clamping unit is simulated to ensure that the clamping voltage can not be greater than the minimum value of the gate oxide breakdown voltage and the source-drain breakdown voltage of the protected device;A normal power-on simulation is performed on the designed clamping unit to ensure that the ESD clamping unit cannot generate a false trigger and generate a large leakage current during normal power-on.The noise immunity capability of the clamping unit was simulated to ensure that when the power supply is affected by noise in the normal process,the clamp unit cannot be turned on and generate a leakage current.2)ESD current drain channels are designed for each combination for possible ESD combinations between different types of PADs.For ESD discharge channels between different combinations,ensure that the designed ESD protection structure has a voltage drop less than the minimum value of the gate oxide breakdown voltage and the source-drain breakdown voltage of the protected device during the discharge of the ESD current.3)Designed a full-chip ESD protection circuit and layout.Considering the effects of parasitic resistances/capacitances on the VDD and VSS power lines to the ESD discharge capability,a reasonable design is made for the number and placement of clamping units between the VDD and VSS power lines to ensure that when ESD occurs,ESD current can be released in time.According to the Design Rule file provided by Foundary,a full-chip ESD protection circuit is provided with a layout design to ensure that the layout has a good anti-ESD capability.