Based On Sige Bicmos Process, The High-speed, Low-power Phase-locked Loop Design

In recent years, the field of electronic technology, in which especially wireless communications, high-speed processors, have a rapid development. As one of the key modules, phase-locked loop is widely used in frequency synthesis of RF transceiver, data recovery in high speed data communication and optical fiber communications and clock generation in microprocessors and digital signal processors. As technology advances, better performance of PLL is demanded, the design of high performance PLL has become a major challenge in wireless communication and high-speed processors. Therefore, research and design of PLL has a positive practical significance.Based on TSMC 0.35um SiGe BiCMOS process, the paper designed a PLL suitable for high-frequency environment. The most mainstream structure: mixed-mode charge pump PLL, is used in this system. Among them, a NP-core cross-coupled structure is used to realize VCO, made full use of advantages the SiGe process, so that the VCO have good performance of phase noise and low power consumption. E-TSPC logic is used in Prescaler design and divder-by-2 circuit is realized with D flip-flop using TSPC logic. In this way, power and speed achieve the best compromise, meanwhile a good compatibility carry out between two different kinds of logic. Phase detector is composed of PFD and CP, dead zoom phenomenon existing in PFD is effectively eliminated by delay unit in the feedback loop, optimization in structure can make the performance of CP more ideal. The entire system has a structure of a fourth-order type two, during the design of PLL, the loop optimization method is employed in design the loop transfer function, which not only broaden the loop bandwidth but also maximize phase margin, therefore, in the way, it can ensure maximum stability of the system, improve the system dynamic performance and optimize the entire system phase noise.The whole system and each block circuit are simulated and verified by the Cadence-Spectre software. The simulation result show that when the power supply is 3.3V and reference input frequency is 75MHz, the output frequency is 2.4GHz and 2.475GHz each, and the time of frequency change is 2.3μs, power dissipation is 49.5mW, therefore all the result satisfy the design requirement.