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A Low Power SAR ADC In Portable Wireless Communication System

Posted on:2018-09-21Degree:MasterType:Thesis
Country:ChinaCandidate:Z ChenFull Text:PDF
GTID:2348330515451634Subject:Microelectronics and Solid State Electronics
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Baseband is a basic module to complete the wireless network in mobile communication.The function of the Baseband chip is divided into sending and receiving.The function of the receiving includes: receiving,filtering,ADC,DSP.With modern wireless communication devices rapidly developed,the frequency of baseband communication is getting higher and higher,and the requirement of ADC becomes tighter.SAR ADC is suitable for integration in baseband chip because of its intrinsic characteristics such as: small size,low power consumption,etc.Traditional SAR ADC sampling rate is difficult to improve because that its timing sequential is controlled by state machine.In recent years,thanks to the invention of asynchronous timing logic module that had become a high-speed SAR ADC standard configuration improve SAR ADC sampling rate.This thesis introduced a 10 Bit 100Msps SAR ADC that based on the SMIC 55 nm CMOS technology.SAR ADC core structure includes: sampling switches,capacitor arrays,dynamic comparator,asynchronous timing logic module,etc.First of all,the structure and design process of pulse modulation circuit,sampling switch,asynchronous timing logic are briefly described.The essentials of the sampling switches and the asynchronous timing logic module are explained.Then,the design of the capacitor arrays and the comparator is described in detail.While the capacitors' mismatch,noise,power consumptions were completely simulated and calculated,as well as comparator offset,noise.This thesis gives a more accurate theoretical model for the comparison speed of the comparator.In this thesis,I described the offset calibration circuit and compared the mainstream offset calibration structure.Eventually designed an offset calibration circuit module.Finally,the simulation results show that this SAR ADC can work at 100 Msps sampling rate.Static and dynamic performance of this SAR ADC is excellent,all absolute values of INL and DNL are less than one LSB.the ENOB of this ADC is able to achieve 9.5 when the input signal frequency is up to 39.4MHz.The power consumption of this SAR ADC is 4.4mW,the FOM is 60.8fJ/Conv.step...
Keywords/Search Tags:SAR, ADC, high speed, low power, asynchronous timing logic
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