Research On High Speed Acquisition And Trigger Technology Of 50GSPS Logic Analyzer

The logic analyzer can intuitively display the logic level of the signal and the timing relationship between the signals on the interface,thereby helping the user to realize the development and testing of the digital system.As the operating frequency of digital circuits becomes higher and higher,logic analyzers need to achieve high-speed acquisition and triggering of high-speed signals to meet test requirements.At present,there is a big gap between domestic logic analyzers in terms of functions such as acquisition and triggering compared with foreign logic analyzers.Therefore,the research on high-speed acquisition and triggering technology can lay a solid foundation for the emergence of domestic high-performance logic analyzers.Combined with the relevant research tasks undertaken in the development of the logic analyzer prototype in this subject,this paper conducts in-depth research on the high-speed acquisition and triggering technology of the logic analyzer:1.Research on high-speed timing analysis technology: Compared with the shift sampling method,the multi-phase sampling method can reduce the sampling clock frequency and improve the signal integrity through clock phase splitting,but it needs to achieve high-precision clock delay.At the same time,due to the loss of high-speed signals in the transmission channel,digital logic level matching circuits and equalizer circuits should be used at the receiving end to achieve high-speed and accurate signal acquisition.2.Research on high-speed state analysis technology: Due to the limitation of the trigger setup time and hold time,the flip-flop circuit cannot realize high-speed state analysis.Based on the high-speed timing analysis scheme,a high-speed state analysis scheme is proposed,which collects external data and external clock at high speed at the same time,and extracts valid data in the data signal at the rising edge of the clock signal.3.Research on extremely narrow glitch detection technology: When the pulse width of the glitch signal is extremely narrow,the edge detection scheme cannot effectively identify the edge of the glitch signal,so the edge detection of the glitch signal is converted into a parallel data edge acquisition interval count,to achieve extremely narrow glitch detection.4.Research on high-speed trigger technology: On the basis of the synchronization of the acquisition circuit,research the design scheme of the high-speed trigger circuit,and realize the synchronization of the trigger signal and the high-speed transmission of the trigger signal.At the same time,the design of high-speed trigger circuit is analyzed in detail by taking edge trigger,glitch trigger and pattern trigger as examples.In this thesis,the key technologies in the high-speed acquisition and trigger circuit are experimentally verified to ensure that the design scheme is correct.At the same time,the main functions and key indicators of the logic analyzer are tested.The test results show that the functions and indicators of the logic analyzer,such as timing analysis rate,state analysis rate,minimum identifiable glitch width,multi-channel synchronization and trigger mode,all meet design requirements.