A 12 Bit 5MHz SAR ADC With Digital Startup Calibration Technology

In the portable systems, data acquisition systems and interface systems, it has the need for signals collected,converted into electrical signals and quantifying the electrical signals.ADC is the key module in the signal acquisition system.Due to the increasing of the requirement for more accuracy and lower power cost,different types of ADCs are also under studying. Comparing with other ADC architectures,successive-approximation-register (SAR) ADCs are well-suited for low-voltage,high-speed applications because of it's simple structure and the use of voltage successive approximation characteristics. In this paper, we will study and design a 12-bit 5MHz SAR ADC based on digital startup calibration with standard CMOS 65nm process.Because of the existence of absolutely error in the process, the mismatch of unit capacitance is about 0.5%. we found that the limiting factor for the ADC precision is the mismatch between the capacitors in the DAC array. In order to reduce the influence on the ADC performance because of mismatch between the capacitors in the DAC array,this paper adopts the digital startup calibration technology to calibrate the capacitor's value after comparing the advantages and disadvantages of different methods of capacitor calibration algorithm.During the system works, it correctes each capacitance's value and updates the result about the capacitor's weight. In the normal statement it will be quantified with the results of the corrected weight to get the correcte code. So the digital startup calibration belongs to the digital domain method that calibrating capacitor's value,and it leads to better results.Based on the matlab modeling, we identify the validity and rationality of the digital startup calibration technology and determines the basic architecture of the 12-bit 5MHz SAR ADC designed in this paper,this paper adopts a non-binary redundant DAC structure. The DAC array uses the segmented structure.According to the structure of redundancy, the comparison errors caused by setting time of DAC or compartor's offset voltage from the correction or normal operation in the high bit's quantization process can be corrected. At the same time, This paper also optimizes the design of the key module and the digital key module. Finally, we finish the layout design and post simulation.Ultimately, under the condition of 5MHz sampling frequency, 1.4MHz input signal frequency, the Hspice simulation method and Candence tools ,results show that the spurious free dynamic range (SFDR) of the ADC is 81.23 dB, the SNDR is 71.15 dB,the effective number of bits (ENOB) is 11.52 bit, the power consumption is 310.05 ?W,and the FOM value is 15.13fJ/ Conv.-s. Meet the design requirements.