Research On Synthesizable Stochastic Analog-to-Digital Conversion Technology Based On Statistical Principles

As integrated circuit designs move toward smaller CMOS process nodes,the cost of power consumption and area decreases,and the circuits operate faster.However analog circuit improvements in performance are greatly constrained,while the reducing of gain and supply voltage causes limited voltage margins and signal swings.And according to the relative errors of process mismatch increasing,it becomes more difficult to design physical layout in analog circuit.In contrast,digital circuit is affected slightly,because digital standard cells can work more stably than analog devices under process variations.And digital circuit layout can be synthesized by automatic placement and routing,showing more significant advantages.As a result that the digitalization of analog circuit has gradually become a research direction.Research on stochastic analog-to-digital conversion based on statistical principals in this thesis,provides a feasible solution to an all-digital ADC.In order to break the inherent analog characteristics of traditional ADC structure,this thesis studies the statistical method of quantification,in which the information is conveyed by statistical data instead of voltage amplitude.On the contrary of traditional analog circuit,the entire design is beneficial from problems of mismatch between devices and offset voltage due to scaling of CMOS processing,on account of obeying statistical principles.The core circuits are designed with digital standard cells,therefore analog amplifiers and passive devices on-chip are completely canceled,so the design is compatible with digital integrated circuits process flow,achieving fast design period and compatibility.In this thesis,core circuits modules,including all-digital comparator and reference voltage generator,are implemented by cross-coupled NAND gates.A stochastic analog-to-digital conversion channel is composed of digital comparators' array in smallest size,reference voltage generators merely controlled by digital codes,a fast coding module,and an inverse Gaussian cumulative distribution function(CDF)calibration module.Several digital comparators are discussed and compared to design a wide-input range channel.A Wallace tree pipeline adder is proposed to process large amounts of 1-bit data rapidly by inserting three,five or seven stages of pipeline according to requirements,with faster speed and less consumptions and area cost than traditional tree adder.Based on look-up table,an inverse Gaussian CDF calibration module can improve linearity of the channel by 5.33dB(SNDR).The structure of multi-channel is proposed,and the calculation of optimal channel spacing is derived in this thesis.Then Simulink behavioral simulation models are built to study single channel features,and to verify that multi-channel can expand the system input range,while improving accuracy and linearity of conversion.The channel layout is generated through automatic placement and routing in accrodance with digital design flow finally.This thesis studies operation principle of a novel synthesizable ADC stucture based on statistical principles.An all-digital ADC is designed under SMIC 180 nm process,and simulation of the system-level Simulink modules shows that ENOB and SNR of an eight-channel stochastic ADC achieves 4.87 bits and 32.56 dB respectively.