The Research And Design Of Low Noise Phase-locked Loop In CMOS Process

With the rapid development of wireless communication technology,the demands for mobile terminals increase continually.Short distance wireless communication protocols such as WiFi,Bluetooth,RFID are widely used.A steady clock signal is required in all communication systems.Phase-locked loops(PLLs)based frequency synthesizer,which are used as local oscillators,are crucial building blocks in wireless transceivers.The clock accuracy affects the overall system performance and therefore a clock generator should have low phase noise for high performance wireless transceivers.This thesis aims to design a low noise phase locked loop.It starts with the introduction of principle,circuit structure and non ideal effect of PLL.And then the influence of loop bandwidth and phase margin on the stability is analyzed.Finally,the phase noise performance is analyzed based on the continuous time linear phase domain model.A phase-locked loop for UHF RFID reader is designed.PLL output frequency of 840 MHz-960 MHz covers the standards of UHF RFID protocol in various regions,which can be used all over the world.Considering protocol requirements for setting time and phase noise performance,the loop bandwidth is set at 40 kHz.UHF RFID reader PLL is implemented in 0.13 ?m CMOS technology.Simulation results show that the output frequency of VCO is from 1.6 GHz to 2.0 GHz,and VCO achieves-112 dBc/Hz phase noise at 100 KHz frequency offset.The setting time of the phase-locked loop is 100?s,and the phase noise is-106 dBc/Hz at 100 kHz and-128 dBc/Hz at I MHz frequency offset.A fast locking sub-sampling phase-locked loop(SSPLL)is proposed.The SSPLL is divider-less in the locked state and thus has no divider noise.The noise contributed from sub-sampling phase detector and sub-sampling charge pump is not multiplied by N2 resulting in very low in-band noise.Dummy sampler can reduce the reference spur introduced by VCO load mismatch.Moreover,in order to shorten the setting time,this thesis proposes a phase frequency detector(PFD)which can adjust the deadzone threshold.The theory of proposed PFD is analyzed and compared with that of traditional fixed deadzone threshold PFD.SSPLL is implemented in 0.18 ?n CMOS technology.Simulation results show that the setting time of PLL is 3 ?s and the reference spur is-79.81 dBc.At frequency offset of 200 KHz,PLL inband phase noise is-124 dBc/Hz.