Broadband Low Phase Noise Frequency Synthesizers V Band

Along with the rapid development of modern communications technology and radar, the frequency source in the system requirements are demanding high performance, and it’s also a trend of the future development. Nowadays, the main performance indicators we considered include phase noise, spectral purity, frequency jumping time, the bandwidth and the frequency stability. Low band frequency source can be achieved by use the ordinary PLL technology, However, such as the V-band in high frequencies, It is difficult to achieve if we not only requires a certain range of bandwidth, but also to satisfy our request of lower phase noise from the frequency source use the PLL technology. Only use the PLL technology to achieve a frequency synthesizer, then achieve the frequency we want by the multiplier. However, the phase noise of the frequency deterioration very serious and can not achieve an idea result which we need. Therefore, based on the sampling phase-locked DRO technology is receiving more attention and application.Compared the sampling phase-locked technology with the PLL technology, the circuit is not only more complex, but also has the narrow bandwidth of the frequency synthesizer. Its disadvantages is the debugging more complicated. The subject is to research the design of V-band wideband low noise frequency synthesizer and the goal of phase noise at50-53GHz indicators is-73dBc/Hz@1KHz,-83dBc/Hz@10KHz,-93dBc/Hz@100KHz. First, we use the advantages of low phase noise and high frequency of the sampling phase-locked frequency synthesizer. Second, we can take the advantages of wideband and low phase noise of the S-and frequency source use the hybrid frequency synthesis technology of PLL, then we can have wideband and low phase noise frequency source by mixer, Multiplier, filter and Amplifier.The theory of the phase-locked loop is introduced and analyzed firstly, and then the expansion capturing circuit is analyzed in the sampling phase-locked circuit and completed the schematic drawing. the minimum phase noise requirements for the PLDRO and the S-band frequency synthesizer can be calculated by the V-band frequency synthesizer, then simulation and design each module circuit, proved it is feasibility from theory. The last stage is to Completed the debugging.