Fpga-based Optical Receiver Data Recovery Circuit Design And Realization

With the development of the communication and information industry, there is an increasing demand on high-speed data transmission, and also on performance of transmitters and receivers. One of the important tasks of the receiver is extracting the synchronous information from the received data which is polluted by noise, and recovering the data exactly. Therefore data recovery circuit (DRC) is the key component in optical transmission systems as well as in other field of digital transmission. The performance of DRC determines the overall performance of the receiver to some extent.At present, there are mainly two kinds of structure of DRC-clock extraction and oversampling. The key point of oversampling DRC is oversample, which adopted a new approach of introducing a local reference clock and increasing the number of sampling clocks to instead of the clock extraction. Compared with DRC with clock extraction, DRC with oversampling has a significant gap in high-speed performance. But DRC with oversampling has a wide-bandwidth, immediate latches capacity, lower latency and higher jitter tolerance. It is easier to be realized by digital way with lower cost. This is a new design methodology of digital-base analog (DBA). If oversampling can be achieved at 622.08 Mb/s or even higher rate by data recovering in logic circuit, it will be used as an IP module instead of the clock recovery chip. It would be a perfect combination of performance and cost.This paper has made a research on basic principle of DRC with oversampling. With the all-digital design method, two different ways of realization of oversampling in low-cost FPGA, and they are oversampling with clock-delay and oversampling with data-delay. By testing and validating, the oversampling DRC with clock-delay has a higher recovery rate which can reach 640 Mb/s. The test results indicate that this DRC can work on 622.08MHz in optical transmission systems and can be applied to STM-4 of SDH System.