Design And Implementation Of Real-time Image Transmission System Based On CDR Technology

In recent years,image real-time transmission is widely used in military,aviation,medicine,communication and other fields.Nowadays,with the increase of high-speed image transmission application scenarios,the research of image real-time transmission system has been paid more and more attention.In order to detect,identify and track the target more accurately and quickly,the infrared focal plane detector commonly used in the military aviation field puts forward high requirements for the speed,real-time and accuracy of image transmission.The traditional parallel image real-time transmission scheme has low transmission rate,poor accuracy,and the walking line is easy to generate thermal noise to interfere with the imaging of infrared focal plane detector.Therefore,in view of the shortcomings of traditional parallel image real-time transmission,the research and development of a high transmission rate,low bit error rate serial transmission system has become the goal of this paper.In view of the problems of high bit error rate and poor stability in the receiver of traditional image transmission system,this paper has carried out relevant research and development work from the following three aspects:first,this paper proposes a high-speed clock synchronization scheme which combines the dynamic phase adjustment with the phase feedback loop,which can effectively ensure the real-time synchronization of sampling clock and working clock,and reduce the register guidance due to the occurrence of metastable state The possibility of sampling error can reduce the error rate of image transmission system;secondly,this paper designs an optimal dynamic selection algorithm of sampling edge,which can dynamically change the selection of sampling edge according to the change of environment,make the sampling edge far away from the edge of data change,and reduce the impact of environment change on the system;finally,based on 8B10B coding,this paper completes the DC balance module It is designed to prevent continuous logic"0"or continuous logic"1"on the transmission line from weakening the signal when sampling at the receiving end,thus causing sampling errors.In view of the low transmission rate of the traditional image transmission system,this paper optimizes from the two aspects of the sender and the receiver:the sender changes the traditional parallel transmission scheme to the serial transmission scheme,and optimizes the parallel to serial conversion structure,which increases the maximum transmission rate of the sender;the receiver adopts the spatial oversampling scheme,which makes use of multiple sampling The phase relationship between the clock and the multi-channel data enables the lower frequency sampling clock to sample serial data several times of its frequency,which maximizes the receiving rate of the receiver.In this design,Verilog HDL is used to design the hardware of the image real-time transmission system,and the function of the system is simulated by Modelsim.Then the prototype is verified based on Xilinx artix-7 FPGA development platform.Finally,the image transmitter is based on HHGrace 90nm The area of consumed logic unit is 112168?m2.The timing and area meet the design requirements of image real-time transmission chip.Through FPGA prototype verification,the highest video transmission rate can reach 1.25Gbps,and the bit error rate is less than 10^-9,which meets the application requirements of the design.