Design Of ADC With A Novel Time-interleaved Sample-and-hold Circuit

Analog to digital converter(ADC)is used for integrated circuit,and is the key circuit to communicate analog signal and digital signal.With the continuous development of digital integrated circuit,a lot kinds of signal is processed in the digital circuit.The faster the speed is,the higher the accuracy of the ADC analog signal is converted to digital signal.At present,there are many kinds of ADC,which are used for different precision and speed working environment.But as people continue to explore the environment,we must constantly develop new and better ADC to meet the needs of the integrated circuit.The ADC structure using time interleaving technology as a new type of ADC circuit structure to improve the circuit sampling rate plays an important role in reducing the performance requirements of single ADC circuit,but the circuit also requires high precision clock,and its multi-channel ADC structrue needs large power consumption.However,in pursue of the performance,researching and designing of multi channel time interleaved ADC structure has become a mainstream trend.In this paper,a new kind of time-interleaved sampling-and-holding circuit in the multi-channel folding-and-interpolating ADC isdesigned.In this structure,the accuracy would be ensured,and the circuit can samle signals in different channel orderly to improve the sampling speed,greatly improves the performance of ADC.Among it,the sampling and holding circuit uses the 4×2 structure with 2 stages and 8 channels structure,which greatly reduces the design difficulty of each channel ADC.The bootstrap switch is used in the sampling-and-holding circuit,so that the linearity of the sampling and holding circuit is improved.The first stage of the pre-amplifiers uses a four inputs with differential structure to reduce the system noise,and the second stage uses a fully differential structure to increase the gain of the pre-amplifier circuit.Pre amplifier network using interpolation technology and resistive mean network technology to improve the performance of the system,through the analysis of the pre-amplifier network,adjust value of the boundary resistance,in order to meet the accuracy requirements of the circuit.The folding and interpolating circuit needs to consider the tradeoff between speed,power and gain.A appropriate structure need to be selected in the high speed comparator to meet the requirements of accuracy and speed.Digital block includes encoder and interface.The output interface circuit suitable for high speed condition is critical to the circuit.Finally,for the design of multi-channel circuit,timing,delay and interval accuracy of different channels need to be accurately considered,and sometimes need to be calibrated.The design is based on TSMC 65 nmLP process.Sapling-and-holding circuit uses a 1.8V voltage,and the ADC core circuit use 1.2V voltage.The total sampling rate of ADC is 2GHz,and the sampling rate of each channel is 250 MHz.the design resolution is 8 bits,at Nyquist sampling frequency simulated SNR is 48.82 d B,the effective number of bits is 7.78 bit,power consumption is 1300 mW.The design achieves the desired objectives.