The Design And Implementation Of VCO In 433MHz CMOS Frequency Synthesizer

Frequency Synthesizer(FS) or Phase Locked Loop(PLL) is the core module of the modern communication system, which directly determines the performance of many wireless or cable RF system. Voltage Controled Oscillator (VCO) as the core module of PLL has always been the hot spot of industry and academia. The design of VCO with constant tuning gain, wide tuning range and low phase noise has always been the challenge for the high-performance PLL.Two VCOs used in the PLL which should cover the three band of 300MHz to 348MHz,400MHz to 464MHz,800MHz to 928MHz and be modulated directly by the digital baseband are designed and implemented in this thesis. Firstly, the research status and design theory of VCO are summarized, including working principle, classification, performance index and phase noise theory, etc. Then the application background of the VCOs is analyzed in detail. The parameter design of the PLL is discussed, so as to confirm the design indexes of the VCOs and how the indexes effect the performance of the whole system. Two VCOs which tuning range is 1.2 GHz to 1.392 GHz throuth divide by four circuit to realizing the band of 300 MHz to 348 MHz, and 1.6 GHz to 1.856 GHz throuth divide by four circuit to realizing the band of 400 MHz to 464 MHz or the divide by two circuit to realing the band of 800 MHz to 928 MHz are completed. In order to resist the frequency offset, technological angle deviation and temperature, the VCOs expand their turning range to 1.0GHz to 1.6GHz and 1.4GHz to 2.1 GHz. The frequency band of each VCO is divided into 16 bands with 4-bit binary control signals and switches of capacitor array. To ensure the output of VCOs keeping a relatively constant swing, the programmable switches which control the tail current from 2.55mA to 3.6mA for the step of 150uA are adopted, In order to complete the application demand of the whole system, in addition to the VCO core circuits, many important periphery auxiliary circuits are also designed carefully, including bias circuit, selection circuit and frequency dividing circuit.The layout is implemented in Cadence Virtuoso after the design work. The design is fabricated by SMIC 0.18?m CMOS technology. Testing scheme circuit is designed and the chip is tested and verified. The measurement results show that the frequency range can cover from 1.0GHz to 1.6GHz and 1.4GHz to 2.1GHz, and the phase noise is below-115dBc/Hz@1MHz.The design meets the requirement of the system.