Design Of High Purity Fractional Frequency-division Phase-locked Loop

Over the last few decades as fast development in electronic and conmmunicational science and technology,the practical use in this field has been promoted faster and faster. Signal generator,which can be called the heart of electronic system,has powerful effect on the whole electronic system.Ithas been a hot question on how to produce a signal generator of low cost, high performance and high stability. That is the technology of frequency synthesize. The performance and cost of the signal generator are directly influenced by the designer to accomplish it in a proper way. Recent years,the fast developing technology of the phase-locked frequency synthesizer has been being one of the main design methods of the signal generator by its superiority.In this paper, the basic structure of PLL frequency synthesizer is researched, then it is introduced that what is the modules'characteristic. In this paper, the basic structure of PLL frequency synthesizer is researched, then it is introduced that what is the modules'characteristic.The paper also introduces the implement of fraction-N frequency synthesizer and the basic structure of sigma-delta modulator. Through the analyzed of fraction-N frequency synthesizer, in order to reduce the phase noise the API techniques was used in the circle.The main work in this article can be divided into two parts:the first part is based on CETC 41's fractional-N PLL, to analyze the key circuits and propose an improved scheme. The second part is focused on the improved scheme. The design of the improved scheme is concentrated in two aspects:1) For phase detection discriminator (PFD), the delay circuit of the original PFD is removed and an inverter is introduced. The reference signal of the PFD is directly connected to the input of inverter. The advantage of doing this is that a charge-discharge balance can be maintained during a phase discrimination cycle.2) For design of compensation circuit, the method of analog phase interpolation (API) is deployed. Based on the theory that fractional-N adder margin is proportional to terminal modulation output, appropriate D/A conversion is chosen to add margin signal to the output of phase detector, so that terminal modulation output can be offset. Noise can be attenuated through this series of work, which basically meet the requirements. The spectrum purity and the performance of fractional-N PLL is improved...