The Timing Budget And Methods Of Optimization In Hierarchical Design

The method of hierarchical design is more and more popular in large-scale and high frequency chip design. The timing budget of each module plays an important role in timing closure. With the increasing of the chip size, on-chip variation becomes increasingly obviously. In high frequency design, clock skew severely restricts the speed of timing closure of the chip, and the delay which is too large in data path will also affect the final timing closure. This paper has done some related research aiming at the key points of restricting the timing closure of the physical design, which based on the placement and routing of a high performance multi-core DSP chip YHFT-XX in 40 nm process. This paper introduces the optimization methods which used in detail.In hierarchical design, the reasonable degree of the timing budget of each module affects the progress of the entire design. This paper has done a certain amount of analysis on the traditional methods of timing budget. Aiming at the shortcomings, according to the characteristics of the design and considering the effect of distance and clock to the timing budget, this paper offers two new methods of timing budget, and proposes the corresponding budget formula. By the deduction of the formula, This paper obtains the influence on timing that generated by clock skew and common path. This paper optimizes the Floorplan of the core under the guidance of timing budget. The length of the critical path is reduced by 19.77%, and then determines the ultimate Floorplan of the design.Reducing the effect of on-chip variation is becoming more and more significant. According to the characteristics of each sub module clock, this paper does a detailed planning to the clock of the core through a detailed analysis of the clock structure. The common path of the clock has increased by 5120 um.In the aspect of clock skew, for the multiplexing module in top-level, this paper simplified the complexity of the problem through the method of classification, optimized the delay and skew of the clock using the method which is similar to H-tree. Among them, the clock latency is reduced by 15.9%.The clock skew is under 15 ps. For the boundary registers, this paper reduced the clock skew to 49 ps by embedding adjustment points, it is reduced by 39.5%,and meets the requirements of the top. For the hard macros and clock gating cells, this paper combined a variety of clock structures and the physical location of hard macros and clock gating cells in different modules, planned the clock and optimized the delay by taking the measure of manual routing. Their clock skews are controlled under 10 ps.For the three modules which partitioned from the top, taking the form of dynamic adjustment to balance their clock skew. This paper solves the adverse effects which brought from clock skew by planning the clock of the design. It has provided the safeguard for the timing optimization in later stage.The delay of the data path is too large that restricts the progress of timing closure. In this paper, we adjust the start point of the reset signal through analyzing the characteristics of the critical path. This measure has optimized the hold time. The maximum violation is reduced by 55.7% and the total number of violation is decreased by 68.7%. The effect of optimization is significant. In this paper, it has optimized the delay by guiding the direction of data flow through manual placing the registers which on key station of the very long data path of cross-module.The effect is obviously that those methods of optimization which aiming at the problem in the chip YHFT-XX. Finally, we achieve the goal of timing closure. At present, the chip has been taped out successfully.