| IC design of the increasing scale of the feature sizes becomes smaller and smaller,the same area can be integrated more number of transistors. Physical design in order tomake full use of human and hardware resources, the design of more than ten milliongeneral hierarchical physical design. The advantages of hierarchical physical design arethe physical design of the various sub-modules can be synchronized and focus on thelocal timing, in order to improve design efficiency and shorten the cycle of designclosure.The traditional hierarchical physical design flow is the first in the top-level netlistdivided, and then when the sub-module clock tree synthesis, using the design methodbased on design (requirements) drive timing diagram (CDTV, the context-driven timingview), ETMI/O boundary timing model and anti-marked back to top-level assembly,followed by the top-level layout process evaluation sub-module port timing (theExtracted timing model) or ILM (Interface Logic model) model to extract thesub-module on the top floor convergenceiteratively to ensure that the timing ofsub-modules and the top level of the final convergence.Related work shows that the top and bottom of the iterative hierarchical physicaldesign, not only spent a lot of manpower and hardware resources has also increased thedesign closure cycle. Firstly, on the top floor, the physical division of the gate-levelnetlist, and then propose a physical design data based on the underlying sub-module forsub-module port timing analysis algorithms, and finally summarized for thesub-modules within the port timing of several optimization methods. Module betweenport timing analysis algorithm data from the physical design of the underlyingsub-module, without extraction ETM or ILM model anti-marked back to the top level,we can estimate no clock skew factors erupted in the port timing modules on the topfloor to meet, thus saving the number of iterations, shorten the design cycle. The mainwork and innovation include:1Summarizing the physical division of the basis of the physical design of thehierarchical top-level netlist and the need to pay attention to the physical division of thetop-level netlist to minimize the sub-module port timing path, thereby also reducing theport timing problems in the sub-module.2Estimating the sub-module port timing can converge on the top floor, reducingthe number of iterations between the bottom and the top-level timing analysis algorithmbased on the underlying sub-module physical design data between the sub-module portat the bottom will be able to. First of all, from the top-level table to match thecorresponding port. Then, from the port of departure to extract the maximum path delay.The final calculation of port clock skew factors, the overall path delay plus the uncertain time, settling time is more than one clock cycle, in order to estimate the sub-moduleport timing whether convergence on the top floor.3In order to reduce the complexity of the algorithm, the article does not considerthe port clock skew factors and analyzed the setup time is met, but the input dataalready exists in the communication clock, and therefore to reduce the port clock skew,this article summarizes several to reduce port clockdeviation method and the experimentproved.4Timing estimates between the port through the port timing analysis algorithmmodules for the port timing are not satisfied in the sub-module This article summarizesthe four sub-module internal port timing optimization method and its implementation.Engineering practice show that this set of analysis and optimization algorithms andprocesses for hierarchical physical design module port timing and port timing problemsbetween the hierarchical physical design module effective, deducing the number ofiterations and shorten the design cycle. Experiments and conclusions of this paper areequally applicable to other projects and hold time analysis and optimization based onthe projects and set-up time analysis and optimization, research methods and analysisalgorithms. |
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