Design Of 12-bit Successive Approximation Register Analog-to-digital Converter

With the development of integrated circuits,system on chip(SOC)and implantable applications are widely used in many fileds,which requires channels for mutual conversion of digital signals and analog signals,and analog-to-digital converters play an important role in transforming continuous analog signals into operational digital signals.Compared with other types of analog-to-digital converters,successive approximation register analog-todigital converters(SAR ADC)are widely used in sensor networks,biomedical,video processing,and wireless communications.Because they have the advantage of low power consumption,high precision,and simple structure.Therefore,high performance SAR ADC has always been a key topic in the research of the integrated circuit industry.This paper aims to design a 12-bit eight channel SAR ADC with a medium sampling rate.The paper first discusses several basic structures of ADC,then designs the circuit structure of several key modules,and finally carries out circuit simulation and layout drawing.First,for the two key point speed accuracy of the comparator,the structure of the three-stage cascade pre-amplifier plus latch is used to increase the speed of the comparator,and the output offset calibration technique is used to ensure the accuracy of the entire comparator.Second,for the digital-to-analog converter module(DAC)design,the segmentation capacitor is constructed by adding an integral transfer function between the high-eight-bit and low-four-capacitor arrays,which reduces the chip area and reduces power consumption,while reducing The unit capacitance reduces the mismatch between the capacitors and improves the capacitance matching when making the layout.At the same time,the use of the extra unit capacitor equivalent to the lower four-bit capacitor reduces the use of the switch to save area.Third,for the sampling circuit,the structure of the transmission gate plus the pseudo switch is used to absorb the excess charge,which reduces the interference of the non-ideal factor on the sampled voltage value.Fourth,in the design of the digital timing control logic,the synchronous timing logic is used to construct the successive approximation logic circuit based on the level flip-flop to control the DAC conversion switch,thereby reducing the power loss.Fifth,in the design of the built-in reference source,a firstorder temperature compensation is performed using a proportional to absolute temperature(PTAT)structure to obtain a stable reference voltage,and a reference current source with a zero-biased bias is constructed by inversely proportional to the absolute temperature(CTAT) structure.A reference current is obtained that is supplied to the bias module to generate a bias current.The power is supplied with 5V voltage,and the circuit is pre-simulated.The result shows that when the sine wave of 154.785 KHz is input at the sampling rate of 2Msps,the effective number of bits(ENOB)is 11.96 bits and the signal-to-noise ratio(SNR)is 73.8d B.The consumption is 3.685 m W.The article is based on the 0.6?m CMOS process layout design,and the electrostatic discharge(ESD)circuit protection of the input port.The post-imitation experiment results show that the effective number of bits is 11.27 bits,the signal-to-noise ratio is 69.6d B,the integral nonlinearity(INL)is 0.334/-0.357,the differential nonlinearity(DNL)is 0.138/-0.269,and the power consumption is 3.74 m W.The value of FOM is 757 f J conversion-step.The simulation results show that the designed ADC has good performance and meets the design requirements.