The Design Of A 12-bit 1M S/s SAR ADC With Redundant Bits

With the advancement of CMOS technology and the improvement of digital signal processing ability,as well as the rapid development of artificial intelligence,5G,IoT,automotive electronics and other fields in recent years,the conversion module between analog signals and digital signals is particularly important.As an indispensable part,the analog-to-digital converter converts the analog signal collected by the front end into the digital signal,and then transmits it to the post-stage digital signal processing circuit.Among them,Successive Approximation Register Analog-to-Digital Converter(SAR ADC)is widely used in medical electronics,automotive electronics,consumer electronics and other fields due to its simple structure,low power consumption,high energy efficiency and easy integration.How to further improve the accuracy of SAR ADC while maintaining its original advantages has always been a research hotspot in the current SAR ADC design field.Based on the research on Successive Approximation Register Analog-to-Digital Converters,this paper designed a 12-bit 1MS/s SAR ADC with redundant bits.First of all,this paper designs a fully differential structure to reduce the influence of non-ideal factors such as charge injection effect,and this structure effectively extends the input dynamic range and improves the conversion accuracy;the design of semi-synchronous timing can reduce the redundancy delay of the comparator to improve the speed of the overall circuit,and at the same time leave enough time for the establishment of the array switch to improve the overall circuit conversion accuracy.Then,this paper focuses on the design of a non-binary segmented capacitor array with three redundant bits to complete the calibration of the quantization error and further improve the accuracy.The array structure reduces the influence of the bridge capacitance in the segmented capacitor array without increasing the number and area of unit capacitors too much,and the structure rationally utilizes the redundancy to complete the calibration of the offset,ensuring the added three redundant bits can provide enough redundant codeword space.After that,this paper focuses on designing an improved monotonic capacitor array switch.By splitting the added three redundant bit capacitors,the same capacitor can be repeatedly operated in the process of successive approximation of the SAR ADC.On the one hand,this method reduces errors introduced in the switching operation process.On the other hand,this structure avoids capacitance mismatch errors caused by operating multiple capacitors,and improves the overall circuit conversion accuracy while reducing power consumption.In addition,this paper also designed a gate voltage bootstrap sampling switch circuit to improve the linearity of the S AR ADC and ensure the accuracy of the subsequent quantization process.In this paper,a dynamic comparator circuit with pre-amplification and post-latch are designed to achieve higher precision and faster comparison speed.SAR logic circuit is designed to reduce the power consumption of digital circuit by using dynamic logic unit structure.A digital calibration circuit is designed to calibrate 15-bit non-binary digital code into 12-bit binary digital code,and to realize algorithm calibration of redundant bits.Finally,this paper designs the layout of the SAR ADC,the key module layout is symmetrical to ensure the matching,and isolation technology is adopted to reduce the influence of parasitic effect and coupling effect.Based on the TSMC 0.18μmrf CMOS process,this paper used the Cadence platform to build the overall SAR ADC circuit.The circuit simulation results show that under the 1.8 V power supply,when the sampling rate is 1M S/s and the input signal is a 236.08 KHz sine wave,the ENOB is 11.31 bits,the SNR is 69.86 dB,the SFDR is 80.81 dB,and the power consumption is 196.2 μW,the core circuit area is 0.09118 mm2.