Design Of Fractional-N PLL Applied To FSK Direct Modulation

Fractional-N PLLs are widely utilized as the FSK direct modulated frequency synthesizers, fulfilling the modulation function of the digital baseband data without up-conversion while synthesizing the carrier frequency because of the characteristics of broad bandwidth, fast-locking, high resolution and low phase noise, etc. The FSK direct modulation based on fractional-N PLLs can behave much better than the classical quadrature modulation, which displays significant research value for the realization of RF transmitters.A fractional-N PLL applied to FSK direct modulation is designed in this thesis. The research status and development trend of direct modulation technique without up-conversion is reviewed. The structure and working principle of the FSK direct modulated frequency synthesizer based on fractional-N PLL is expounded and the loop compensation technique with digital auto-calibration is analyzed in detail. The system-level design of fractional-N PLL applied to FSK direct modulation is accomplished on the basis of closed-loop ?? modulation and the performance indicators related are defined. For the design of ?? modulator, a basic 3-order structure is defined after functional verification by using Matlab/Simulink, and a new 3-order structure with feedback and feedforward mixed based on the W. Rhee 3-order single-loop feedback structure is designed, improving the noise-shaping performance and releasing the linearity confinement of other blocks in the loop. And on the basis of classical phase-switching structure, the design of multi-modulus programmable divider with phase-switching directly controlled by the pulse-swallow counter is fulfilled, realizing the division function in modulus of 56-255 and by step 1. Compared with the classical phase-switching structure, the separate circuit and signal which respectively control phase-switching and division mode is both removed in this divider designed, consequently facilitating the divider structure simplified and the whole power dissipation of divider reduced.The fractional-N PLL applied to FSK direct modulation, including schematic and layout, is accomplished with 1.8V supply and in SMIC 0.18?m CMOS process, with the post-simulation and chip test fulfilled consequently. The simulation results show that the settling time is less than 50?s and the output frequency covers 387MHz?464MHz. Meanwhile the test data show that the phase noise can be below-110dBc/Hz@1MHz with a resolution of 400Hz.