Design Of Fractional Frequency Divider For 60GHZ Fractional-N PLL

Inspired by the Google innovative application of 60 GHz band on the gesture radar, there emerges the 60 GHz short range radar applications. In particular, with the advance of the CMOS speed and integration level, the 60 GHz integral communication and radar system become possible. As a vital part in the system, the spur and phase noise performance of the Fractional-N phase-locked-loop (PLL) is very crucial. As a key building block of the Fractional-N PLL, the fractional frequency divider limits the PLL spur performance, and it has great research value. Therefore this thesis focuses on the design of the fractional frequency divider for the system.Basically, the fractional frequency divider consists of the pre-divide-by-2 frequency divider, the phase selector, the auxiliary logic circuits, the multi-modulus frequency divider and the Delta-Sigma modulator (A.K.A. DSM in this thesis). To improve the circuit performance, this thesis follows the system and the circuit co-design ideal. At the system level:1) based on the linear model of the PLL in the phase locked mode, the impact of the fractional frequency divider on the PLL is analyzed; 2) the DSM is modeled using Matlab, and the modeling and simulation of the full fractional frequency divider is undertaken. At the circuit level,1) to reduce its power consumption and to increase the working frequency range, the static C2MOS logic is used to realize the pre-divide-by-2 frequency divider,; 2) the phase selector is realized using the transmission-gate circuit, and the phase lag switching structure is proposed? to reduce the impact of the phase delay on the circuit function; 3) the auxiliary logic circuits provide the pre-control code, reducing the digital control unit speed and power consumption; 4) To reduce dc power consumption, with static CMOS logic, the multi-modulus frequency divider is realized with 6-stage cascading 2/3 two-modulus frequency dividers, and achieves 16-127 dividing range; 5) the output signal is retimed by the retiming circuit, effectively reducing the phase noise; 6) to relax the limit of the DSM quantization noise on the PLL loop-bandwidth, the notch-filtering is introduced in the MASH 1-1-1 structure.In this thesis, based on the 65nm CMOS techniques, the high speed circuit, like pre-divide-by-2 and the multi-modulus frequency divider, and DSM are designed with the full-custom and the synopsis digital synthesis process, respectively, increasing the circuit performance and design efficiency. The core area of the fractional frequency divider is 240um×420um. The post-layout simulation proves the divider function. The circuit performance is summarized as follows:1) the highest working frequency:8.5GHz@ the slow-slow process corner; 2) the frequency dividing range:32-256; 3) the step resolution:0.5; 4) the power consumption:<8mA@1.2V supply. Clearly, these results meet the system requirements. The multi-modulus frequency divider has been fabricated and tested. The test results show that it works correctly from 1 to 7GHz, and consumes <3mW power at 3GHz input frequency, meeting the system requirements.