Sigma Delta, Decimal Frequency Synthesizers Number Of Small And Medium Frequency Divider Research And Design

In the communication system, the precise local oscillation signal is provided byfrequency synthesizer (FS). With the advantages such as low phase noise, fast lockingtime and short channel spacing, Sigma-Delta fractional-N phase-lock-loop frequencysynthesizer(ΣΔ PLL-FS) has become the mainstream in design and application,However, these advantages are gained by fractional divider used in it. This thesis hasthe following achievements based on the fractional divider used in ΣΔ PLL-FS.1. To deal with the complexity of loop parameters calculation, a new approachfor calculating the parameters of loop filter are proposed, and its matlab program codeis also given.2. For lacking how to implement a Σ-Δ modulator in most papers at present, theprocess of implementing a three order MASH1-1-1is addressed, especially the20bitcarry-look-ahead adder.3. For programmable divider, two different plus-swallow counters(asynchronism reset PS counter and synchronism load PS counter) are designed.Because of race and hazard,it is found that the asynchronism PS counter is impossibleto be used in Σ-Δ PLL-FS.4. To connect the Σ-Δ modulator and programmable divider, an interface circuitis designed. The fractional divider is implemented in0.35μm1P5M CMOS process.The layout is600μm×330μm. The post layout simulation shows that the highestoperating frequency of this fractional divider is2.1GHz, and the division modulusrange is80~107.