Design Of A Fractional Divider Based On Δ∑ Modulation Technology

Fractional-N frequency synthesizers are widely used in all forms of radio communications chip, because it has the advantage of fast locking, high frequency resolution and low phase noise, etc. The fractional-N divider as one of the core modules of phase lock loop, realization of programmable and continuous change of the frequency division, is the premise and key to achieve high performance frequency synthesizer.A Fraction-N Divider is designed based on the technique of △∑ Modulator in this thesis. The research status of fractional technology is reviewed. Embarks from the system level, the basic principle of the decimal frequency division were analyzed and the △∑ modulator performance optimization techniques is summarized. In order to assess the phase noise of the divider contribution to the total output phase noise, the noise of the divider model is established. For delta-sigma modulator design, using Simulink tools analysis and modeling to determine the basic structure and order of the delta-sigma modulator. In this thesis, an improved architecture is proposed. It adopts the combination of Nested Mixed-Radix and HK-MASH to improve the output spectrum performance and eliminates the frequency error which is introduced by finite word length effect. For the design of multi-mode programmable frequency divider, adopting the combination of SCL structure and TSPC structure way to reduce the power consumption of divider, a low power multi-modulus dividers based on 2/3 dividers cell is designed according to the index requirements. Its divider ratio range reached 32～127.5, and the division is half-step to quantization noise suppression.The entire Fractional-N divider schematic and layout of this thesis are designed and post-simulated using SMIC 0.18μm CMOS technology. The simulation results show that the locking time of frequency synthesizer is below 10μs; the operating frequency range of the Fractional-N divider is from 1.5GHz to 2.8GHz; the frequency resolution is 25Hz; the phase noise is below-135dBc/Hz@10KHz across all bands; the current consumption is less than 2.4mA under the 1.8 V supply voltage, which meets the design requirement.