Design Of Low Power Consumption Ring Voltage Controlled Oscillator

The clock data recovery circuit(CDR)is the core module of the Serdes system,and the voltagecontrolled oscillator is the key module of the clock data recovery circuit.Therefore,the power consumption of the voltage-controlled oscillator accounts for a large proportion of the power consumption of the entire system.The entire phase-locked loop system is required to comply with the JESD204 B protocol and reach a data transmission rate of 12.5Gbps.CDR circuit adopts 1/4 rate,ring voltage-controlled oscillator realizes multi-phase output,and the frequency reaches 3.125 GHz while meeting low power consumption level is the focus and difficulty of research.A four-stage pseudo-differential ring voltage-controlled oscillator is designed in this thesis.In order to reduce power consumption and output eight quadrature phase waveforms,multi-channel technology,ie feedforward technology,is used to add two sets of cross-coupled pairs of tubes,namely NMOS cross-coupled pair and PMOS Cross-coupled pairs.Since the rise time of the output waveform is greater than the fall time,the design of a low-power resistance enhanced pseudo-differential delay unit structure is improved,which reduces the rise time of the output waveform by increasing the overdrive voltage value of the feedforward MOS tube.Obtain a symmetrical output waveform,speed up the output port voltage waveform flip,and reduce phase noise.Use varactor array for fine frequency adjustment,and differential capacitor switch array for coarse adjustment.The self-biased buffer structure is adopted in this article to reshape the output waveform and increase the output swing.Based on the TSMC 40 nm CMOS process,In this thesis,a four-stage pseudo-differential ring voltagecontrolled oscillator with low power consumption and low phase noise is realized,and its layout design and post-simulation are carried out.The layout area is 266um×335um.When the power supply voltage is 1.1V,the current is 3.8m A,and the oscillation frequency is 3.06GHz?3.14 GHz.When the frequency is 3.125 GHz,the phase noise is-97 d Bc/Hz@1MHz,and the Fo M value is-160.7d Bc/Hz.