Research On The Method Of Power Optimization In The Back-end Design Of High Performance DSP

With the improvement of integration,the number of transistors per unit area increased exponential,power consumption caused by advanced technology is becoming serious.Power consumption of the chip is an important factor considered by designer.In the back-end design,physical unit and interconnect are different from the logic design of RTL stage,increase power consumption makes design difficult to meet the requirements.Combining with FT-MX chip,this thesis researched the methods of reducing power consumption from the aspects of design method,module layout,clock tree structure and cell used etc.FT-MX chip uses hierarchical design,divided top into ten peripherals.The design of memory in peripheral directly affect performance and power consumption of the chip.Aiming at the problem of memory with low performance and high power consumption,the thesis customized a small capacity SRAM with 8T structure and optimized the clock circuit to eliminate output glitch.Compared with previous memory,area reduced by50%,power consumption reduced by 45% and the timing also improved.In physical design,the high local density,insufficient wiring resources will increase power consumption,the limitation of max transition and max capacitance also will increase power consumption,minimum cost to astringe design is the goal of the back-end designer.This thesis researched the source of power consumption in physical design and put forward the following four kinds of optimization method:First,aiming at the increased power caused by unreasonable cell layout,flip-flop-bonding(FF-bonding)is usedin this thesis.This method extracts the location of registers and rearranges to guide the combinational logic,groups the register generate clock tree to reduce wire length.Through this method,the design area reduced by 2.7%,clock skew reduced 73 ps,power consumption reduced by 3%.Second,aiming at the increased power caused by unreasonable clock tree structure,grading CTS is usedin this paper.This method generates register and clock-gating'clock tree in stages and adjusts the location of long latency to reduce clock skew.Through this method,unit area decreased by 4.2%,design power consumption reduced by 6.3%,the decrease of clock skew speed up the convergence.Third,aiming at the increased power caused by cell with unreasonable threshold and size,the optimization of non-critical path is usedin this paper.Positioning the cell in non-critical path,this method by replacing unit threshold and size to optimize the power consumption.Through this method,the max violation reduced 18 ps,the power consumption reduced by 1.2%.Fourth,aiming at the increased power caused by unreasonable register type,register replacing is usedin this paper.This method researched the use of register type indifferent timing path and combined with new register replace in design to optimize power consumption.Through this method,power consumption reduced 28.1% at most.