ASIP Design With Partial Reconfigurable Function Units

Along with the progress of technology, data processing demand represented by data intensive applications become more and more complicated. The traditional design methods, such as GPP(General Purpose Processor) or ASIC(Application Specific Integrated Circuit, has more and more serious limitation. GPP has lower performance, while ASIC, which provides better performance, cannot be modified after the completion of manufacture, lacking of flexibility.With reconfigurable functional units, The ASIP(Application Specific Instruction Set Processor) has higher flexibility and better performance. It also realize the internal FPGA logic resources time-division multiplexing, making maximum use of the resources. Dynamic partial reconfiguration is characterized by the system under the premise of normal operation, on-line modification part dynamic module function, meanwhile other modules of the system operation without interference, that can save hardware resources and enhance the system flexibility.The paper uses Xilinx Virtex-6 XC6VSX315T chip, built on the platform to design an ASIP with reconfigurable functional unit. The ASIP can realize the reconfiguration function, with the arctangent arithmetic operations and square root arithmetic operations. The main results of the study include:(1) discussed the research background and significance, then setup a reliable dynamic partial reconfiguration design method, including the circuit function described in Verilog HDL, design static module and dynamic reconfigurable module, implement configuration and verify bit files.(2) designed the circuit of arctangent arithmetic operations, with CORDIC theory and the pipelined design method. It can achieve arctangent arithmetic operations, by shift operations and subtraction operations., and error within the allowable range.(3) realized the ASIP design, which has reconfigurable functional units. The ASIP can achieves the basic operations, according to the requirements of the instruction set, also it realized reconfiguration between the arctangent arithmetic operations and the square root operation. Simulation showed that the system can realize time-division multiplexed of hardware resources, and it can improve the utilization of logic resources.