Research On Reconfigurable System-on-Chip For Supporting Function Level Transparent Hardware Programming

Reconfigurable System-on-Chip (RSOC) typically includes microprocessor, reconfigurable computing unit, memory and so on. The microprocessor is used to implement the order and non-critical code, and the highly parallel and computationally intensive applications can be placed on reconfigurable unit as a hardware accelerator implementation. Such a microprocessor and reconfigurable hardware module mixed structure combines the advantages of both GPP(General-Purpose Processor) and ASIC(Application Specific Integrated Circuits), providing the hardware efficiency and software flexibility in one platform, hence becomes a promising solution for the future embedded computing.For reconfigurable system-on-chip, the hardware is no longer fixed, but can be as flexible as software. Difference between hardware and software is reduced, the extent of fusion increased. This enhances system performance at the same time it also brings up the difficult design. Because designers will need to know the architectural and physical details of the reconfigurable device, manage the configuration of hardware accelerators, as well as the communication between hardware and software, which is great burden for the designers and may decrease the development efficiency and greatly hindered the reconfigurable system-on-chip in real life applications.To address the above issue, this paper research and implement a reconfigurable System-on-Chip for Supporting function level transparent hardware programming. In this system, the hardware accelerators are described as hardware functions which constitute a hardware function library. It hides the details of hardware and provides an easy-to-use interface to the designers. In order to enhance the portability, the hardware functions are modular designed. And the parts of the hardware functions which are closely related to underlying hardware and operating system are designed as separate modules. So, a reconfigurable manager and a hardware function driver manager which used to manage the dynamic configure and the driver of the hardware functions was developed based on Linux kernel. Setup a reliable module-based dynamic partial reconfiguration design method for Xilinx Virtex-II Pro Series FPGAs, including the establishment of the initial hardware platform, the partitioning and design of static and reconfigurable module, module active and system assembly.Finally, a run-time dynamic partial reconfigurable system prototype is developed based on Xilinx Virtex-II Pro XC2VP30 platform for the graphics applications.In order to verify the scheme, we design some hardware functions to test this system. The results show that the system works properly. By adopting the transparent programming model, what programmers need to do is to call a hardware function while the system automatically reconfigure the corresponding accelerator and controls it to finish the computing task. This is helpful to increase the design efficiency of whole system. The experimental results show that by calling the appropriate hardware function to replace the software function, the system's computing power has been enhanced.