Reconfigurable processing engines for area and power efficient arithmetic and matrix operations

Embedded systems used in real-time applications require low power, less area and high computation speed. Embedded processors must cope with this high data rate and process the incoming data based on specific application requirements. Even though there are many different application domains, they all require arithmetic operations that compute the desired values fast using low power, high precision, larger range of operation and reconfigurable behavior. The type of necessary arithmetic functions and matrix operations may vary greatly among different applications. The RTL-based design and verification of one or more of these functions may be time-consuming. Some High Level Synthesis tools reduce this design and verification time but may not be optimal or suitable for low power applications.;We developed a Reconfigurable Processing Engine (RPE) to improve design time and reduce the verification process, but the key point is to use a unified design that combines some basic operations with more complex operations to reduce area and power consumption. RPE generates higher accuracy and a larger range by using a unified arithmetic block system, eliminating all redundant components without compromising overall speed. There are also special transformations that must be used in key algorithms. Hence, this unified area-efficient reconfigurable processing platform offers basic and advanced matrix operations. These operations range from simple addition operations to more complex matrix operations such as LU, Cholesky, and QR factorization and Eigen value calculations. We used some of the most commonly known algorithms to implement these functions and factorizations and modified them to reduce the hardware for low power and accurate operations. To reduce the area of the design and increase the accuracy, a reusable hardware principle and smart control system are used.;Our results indicate that using the RPE from the simple design to more complex systems can improve design time by reducing the verification time up to 75%. The RPE generates structurally based RTL code, a testbench and gives designers more control. RPE provided up to 64% area reduction and reduce verification time up to 70%. The RPE uses current and optimized algorithms to implement designs for better accuracy at a better throughput.