Hardware Modeling Of High Precision Floating Point Sine/cosine And Arctangent Function Units

In the field of digital signal processing such as navigation and radar,a large number of sine-cosine and arctangent function calculations are required.At present,the main method is to use FPGAs to perform parallel operations.The hardware desig n scheme mainly includes lookup-table method,polynomial approximation method and CORDIC?Coordinate Rotation Digital Computer?algorithm.With the improvement of accuracy requirements,the hardware consumption of the table lookup method and polynomial approximation method increases exponentially.CORDIC algorithm can be achieved by shifting and addition to calculate trigonometric function and transcendental function,which is the preferred hardware algorithm for high-precision sine-cosine and arctangent function calculations.At present,the calculation accuracy of sine-cosine and arctangent functions mainly includes fixed-point,single-precision floating-point,and double-precision floating-point.There are few studies on the implementation of 128-bit floating-point computing hardware.Based on the CORDIC algorithm,this paper conducts a hardware structure study of 128-bit high-precision floating-point sine-cosine and arctangent function.The research in this paper is of great value for the requirements of high-precision fast hyperfunctions such as radar,navigation,and weather.In order to reduce the number of iterations and improve the operation speed,this paper designs a four-step parallel-branch-iterative CORDIC algorithm for sine-cosine and arctangent function calculation.Based on the traditional single-step iteration of CORDIC,it is improved to complete the four-step iteration calculation for each cycle.In each clock cycle,16 possible cases of x,y,and z are calculated in parallel to predict the sign factor of the next four-step iteration.To achieve the 113-bit accuracy of the 128-bit floating-point standard,the traditional CORDIC algorithm needs to go through 113 clock cycles,and the improved four-step parallel-branch-iteration CORDIC algorithm only needs 32 clock cycles to complete the calculation.The paper designs the hardware structure of sine-cosine and arctangent functions in parallel.The hardware structure of the floating-point sine-cosine and arctangent function arithmetic unit each includes three modules: pre-processing module,fourstep parallel-iteration module,and post-processing module.The pre-processing module is responsible for processing the abnormal angle of the input and converting the input floating-point angle into the convergence range that can be calculated by the CORDIC algorithm.The four-step parallel-iteration module is the core module that implements the improved four-step parallel CORDIC algorithm for hardware Realization.The post-processing module includes leading zero detection,normalization,and combines the results of quadrant mapping to convert the fixed-point calculation results into standard floating-point outputs.The hardware modeling in the thesis was written using Verilog.The Modelsim platform was used to verify the design and finally synthesized under the TSMC65 nm process.During the test,the Python platform was used to generate 128-bit floatingpoint random data,and the ideal calculation results were generated.A lot of data comparison was made with the simulation results in this hardware modeling.The test results show that for the sine and cosine function,the maximum calculation error does not exceed 1 bit in the range of the input numerical index [2^-11,213].The arctangent function floating-point arithmetic unit has a maximum error of no more than 1 bit when the index ratio of the input value y/x is greater than 2-10,and both can achieve high precision requirements.The calculation period of the two arithmetic units is only 32 cycles.At the operating frequency of 500 MHz,the hardware area of the sine and cosine function unit is about 0.75 mm²,the hardware power consumption is about 75.57 m W.The hardware area of the arctangent function unit is about 0.63 mm²,the hardware power consumption is about 40.65 m W.In summary,this design achieves the expected goal and completes the hardware modeling of high-precision floatingpoint sine-cosine and arctangent function units.